Appendix A: SPICE Model of Power MOSFETs

A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.

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Matlab/Simulink Modeling of SiC Power MOSFETs

International Review of Electrical Engineering (IREE) ◽

10.15866/iree.v9i4.2909 ◽

2014 ◽

Vol 9 (4) ◽

pp. 671 ◽

Cited By ~ 3

Author(s):

Paolo Giammatteo ◽

Concettina Buccella ◽

Carlo Cecati

Keyword(s):

Matlab Simulink ◽

Power Mosfets

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Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0350 ◽

2014 ◽

Author(s):

Ian Kearney ◽

Hank Sung

Keyword(s):

New Product Development ◽

Silicon Oxide ◽

Low Voltage ◽

Photon Emission ◽

Electrical Characterization ◽

Power Mosfets ◽

Low Leakage ◽

A Cell ◽

Thermographic Analysis ◽

Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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ОСОБЕННОСТИ ЭКСТРАКЦИИ SPICE-МОДЕЛЕЙ ТРАНЗИСТОРОВ ДЛЯ ТЕХНОЛОГИЙ КНИ ГЛУБОКОГО СУБМИКРОННОГО УРОВНЯ

Nanoindustry Russia ◽

10.22184/1993-8578.2020.13.3s.680.683 ◽

2020 ◽

Vol 96 (3s) ◽

pp. 680-683

Author(s):

А.В. Нуштаев ◽

А.Г. Потупчик

Keyword(s):

Process Design ◽

Development Process ◽

Dynamic Parameters ◽

Mos Transistors ◽

Spice Model

Разработаны тестовые структуры для экстракции и верификации статических и динамических параметров SPICE-моделей транзисторов. Проведена экстракция SPICE-моделей МОП-транзисторов А-типа в рамках разработки комплекта средств проектирования для технологии КНИ-180. Проведена верификация статических и динамических параметров полученных моделей транзисторов. The paper highlights test structures for the extraction and verification of static and dynamic parameters of the transistor SPICE model. The SPICE models of A-type MOS transistors for development process design kit for S0I180 technology have been extracted. Verification of static and dynamic parameters of the obtained transistor models has been carried out.

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Critical Technical Issues in High Voltage SiC Power Devices

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.895 ◽

2008 ◽

Vol 600-603 ◽

pp. 895-900 ◽

Cited By ~ 14

Author(s):

Anant K. Agarwal ◽

Albert A. Burk ◽

Robert Callanan ◽

Craig Capell ◽

Mrinal K. Das ◽

...

Keyword(s):

Threshold Voltage ◽

Carrier Mobility ◽

Negative Charge ◽

State Of The Art ◽

Power Devices ◽

Power Mosfets ◽

Large Numbers ◽

Technical Issues ◽

The Difference ◽

Difficult Issue

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.

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