Characteristics of PEALD–Hafnium Dioxide Films and their Application to Gate Insulator Stacks of Photosynaptic Transistors

2021 ◽  
pp. 2101061
Author(s):  
Jieun Kim ◽  
Jung Wook Lim ◽  
Jeahee Lee
Keyword(s):  
Hafnium Dioxide ◽  
Gate Insulator

Investigation of ferroelectrics using conventional and in situ electron microscopy

1994 ◽  
Vol 52 ◽  
pp. 586-587
Author(s):  
V. Saikumar ◽  
H. M. Chan ◽  
M. P. Harmer
Keyword(s):  
Nonvolatile Memory ◽  
Ferroelectric Materials ◽  
Gate Insulator ◽  
Sensors And Actuators ◽  
In Situ Electron Microscopy ◽  
Ferroelectric Domains ◽  
Domain Boundaries ◽  
Domain Interactions ◽  
Memory Applications

In recent years, there has been a growing interest in the application of ferroelectric thin films for nonvolatile memory applications and as a gate insulator in DRAM structures. In addition, bulk ferroelectric materials are also widely used as components in electronic circuits and find numerous applications in sensors and actuators. To a large extent, the performance of ferroelectric materials are governed by the ferroelectric domains (with dimensions in the micron to sub-micron range) and the switching of domains in the presence of an applied field. Conventional TEM studies of ferroelectric domains structures, in conjunction with in-situ studies of the domain interactions can aid in explaining the behavior of ferroelectric materials, while providing some answers to the mechanisms and processes that influence the performance of ferroelectric materials. A few examples from bulk and thin film ferroelectric materials studied using the TEM are discussed below.Figure 1 shows micrographs of ferroelectric domains obtained from undoped and Fe-doped BaTiO3 single crystals. The domain boundaries have been identified as 90° domains with the boundaries parallel to <011>.

Influence of Si Surface Roughness on Electrical Characteristics of MOSFET with HfON Gate Insulator Formed by ECR Plasma Sputtering

2014 ◽  
Vol E97.C (5) ◽  
pp. 413-418 ◽  
Author(s):  
Dae-Hee HAN ◽  
Shun-ichiro OHMI ◽  
Tomoyuki SUWA ◽  
Philippe GAUBERT ◽  
Tadahiro OHMI
Keyword(s):  
Surface Roughness ◽  
Gate Insulator ◽  
Electrical Characteristics ◽  
Ecr Plasma ◽  
Plasma Sputtering

Investigation of Switching Mechanism in HfO2-Based Oxide Resistive Memories by In-Situ Transmission Electron Microscopy and Electron Energy Loss Spectroscopy

2017 ◽  
Author(s):  
T. Dewolf ◽  
D. Cooper ◽  
N. Bernier ◽  
V. Delaye ◽  
A. Grenier ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Energy Loss ◽  
Electron Energy ◽  
Electron Energy Loss Spectroscopy ◽  
Hafnium Dioxide ◽  
Switching Mechanism ◽  
Transmission Electron ◽  
Electron Energy Loss

Abstract Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.

Low-Temperature Formation of SiNx Gate Insulator for Thin-Film Transistor Using CAT-CVD Method

1998 ◽  
Vol 508 ◽  
Author(s):  
A. Izumi ◽  
T. Ichise ◽  
H. Matsumura
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Silicon Nitride ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
State Density ◽  
Gate Insulator ◽  
Catalytic Chemical Vapor Deposition ◽  
Silicon Nitride Films

AbstractSilicon nitride films prepared by low temperatures are widely applicable as gate insulator films of thin film transistors of liquid crystal displays. In this work, silicon nitride films are formed around 300 °C by deposition and direct nitridation methods in a catalytic chemical vapor deposition system. The properties of the silicon nitride films are investigated. It is found that, 1) the breakdown electric field is over 9MV/cm, 2) the surface state density is about 1011cm−2eV−1 are observed in the deposition films. These result shows the usefulness of the catalytic chemical vapor deposition silicon nitride films as gate insulator material for thin film transistors.

Optimized Al-doped TiO2 gate insulator for metal-oxide-semiconductor capacitor on Ge substrate

2021 ◽  
Author(s):  
Dong Gun Kim ◽  
Cheol Hyun An ◽  
Sanghyeon Kim ◽  
Dae Seon Kwon ◽  
Junil Lim ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Tio2 Film ◽  
Single Layer ◽  
Atomic Layer ◽  
Metal Oxide Semiconductor ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
High K ◽  
Metal Oxide Semiconductor Capacitor

Atomic layer deposited TiO2- and Al2O3-based high-k gate insulator (GI) were examined for the Ge-based metal-oxide-semiconductor capacitor application. The single-layer TiO2 film showed a too high leakage current to be...

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

scholarly journals Application of Scattering Parameters to DPL Time-Lag Parameter Estimation at Nanoscale in Modern Integration Circuit Structures

Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4425
Author(s):  
Mariusz Zubert ◽  
Zbigniew Kulesza ◽  
Mariusz Jankowski ◽  
Andrzej Napieralski
Keyword(s):  
Integrated Circuits ◽  
Time Lag ◽  
Estimation Procedure ◽  
Micro Electro Mechanical System ◽  
Hafnium Dioxide ◽  
Parameters Estimation ◽  
Phase Lag ◽  
Scattering Parameters ◽  
Materials Used ◽  
Temperature Time

This paper presents the methodology of material parameters’ estimation for the dual-phase-lag (DPL) model at the nanoscale in modern integration circuit (IC) structures. The analyses and measurements performed were used in the unique dedicated micro-electro-mechanical system (MEMS) test structure. The electric and thermal domain of this structure was analysed. Finally, the silicon dioxide (SiO2) temperature time-lag estimation procedure is presented based on the scattering parameters measured by a vector network analyser for the considered MEMS structure together with the 2-omega method. The proposed methodology has the ability to estimate the time-lag parameter with high accuracy and is also suitable for the temperature time-lag estimation for other manufacturing process technologies of ICs and other insulation materials used for integrated circuits such as silicon nitride (Si3N4), titanium nitride (TiN), and hafnium dioxide (HfO2).

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