As on-chip device densities increase and active device dimensions shrink, signal delays and noise increase due to capacitive coupling and crosstalk between the metal interconnections. Since delays, noise, and power consumption all depend critically on the dielectric constant of the separating insulator, much attention has focused recently on replacing standard silicon dioxide with new intermetal dielectrics (IMDs) having dielectric constants considerably lower than conventional oxide (k = 3.9–4.2). On-chip silicon dioxide insulators are currently deposited by gas-phase techniques such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. Silicate films may also be formed at lower temperatures by sol-gel procedures. In the sol-gel process, typically an orthosilicate ester is hydrolyzed with water. This often occurs in an organic solvent to form a soluble, partially condensed polymer (sol) that can be spun on a substrate to produce a solvent-containing film. Subsequent solvent removal and curing results in the silicate film. The process involves hydrolysis to generate polyfunctional silanols followed by condensation polymerization to eventually yield a gel. Since both processes involve the substantial loss of volatile materials, considerable shrinkage occurs (75–85% is typical). Inhomogeneity of shrinkage or shrinkage on constraining substrates can often lead to cracking unless the films are very thin (often <1 μm). In the sol-gel process, a variety of techniques are employed to avoid capillary-driven cracking forces, including (1) very slow drying, (2) drying with supercritical fluids, or (3) chemically controlled condensation.
Nanoscale Silicon Dioxide Prepared by Sol-Gel Process