Threshold voltage stability comparison in AlGaN/GaN FLASH MOS-HFETs utilizing charge trap or floating gate charge storage

2011 ◽  
Vol 9 (3-4) ◽  
pp. 864-867 ◽  
Author(s):  
Casey Kirkpatrick ◽  
Bongmook Lee ◽  
YoungHwan Choi ◽  
Alex Huang ◽  
Veena Misra
2004 ◽  
Vol 830 ◽  
Author(s):  
S. Kolliopoulou ◽  
D. Tsoukalas ◽  
P. Dimitrakis ◽  
P. Normand ◽  
S. Paul ◽  
...  

ABSTRACTIn this work, we demonstrate a MISFET memory device that incorporates a monolayer of Langmuir-Blodgett (LB) deposited gold nanoparticles as floating gate charge storage elements. The FET device is fabricated on a SOI substrate using conventional silicon processing. The nanoparticle layer is separated from the channel area of the FET with a 5 nm thermal SiO2 layer and is isolated from Al gate contact with a LB-deposited organic insulator layer. The memory effect is tested using voltage pulses on the gate of the device and monitored through drain current measurements. The nanocrystals can be charged either from the channel through the thermal oxide layer by applying pulses smaller than 5 V or from the gate through the organic insulator for higher voltage depending on the pulse duration.


Micromachines ◽  
2019 ◽  
Vol 10 (10) ◽  
pp. 643 ◽  
Author(s):  
Amjad Al-shawi ◽  
Maysoon Alias ◽  
Paul Sayers ◽  
Mohammed Fadhil Mabrook

To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).


2019 ◽  
Vol 25 (7) ◽  
pp. 433-439 ◽  
Author(s):  
Seiichi Miyazaki ◽  
Katsunori Makihara ◽  
Mitsuhisa Ikeda

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