P‐100: Improvement of Film Profile and Device Performance with Different HIL Inks for High‐Resolution Display in Solution‐Processed OLED

2021 ◽  
Vol 52 (1) ◽  
pp. 1455-1458
Author(s):  
Jun Ho Youn ◽  
JeongKyun Shin ◽  
SangBin Lee ◽  
Heumell Baek ◽  
HyoDae Bae
Author(s):  
Nicholle R. Wallwork ◽  
Masashi Mamada ◽  
Atul Shukla ◽  
Sarah K. M. McGregor ◽  
Chihaya Adachi ◽  
...  

Hyperfluorescent organic light-emitting diodes (OLEDs) has allowed remarkable device performances to be achieved using fluorescent emitters. Superior device performance has been realised using thermally evaporated emissive layers. However, for future...


2015 ◽  
Vol 3 (48) ◽  
pp. 12403-12409 ◽  
Author(s):  
Haijun Zhang ◽  
Qian Zhang ◽  
Miaomiao Li ◽  
Bin Kan ◽  
Wang Ni ◽  
...  

Solution-processed carbon dots (CDs) as the electron transport layers (ETLs) significantly enhanced device performance (Jscand FF) and lifetime.


2012 ◽  
Vol 25 (6) ◽  
pp. 894-898 ◽  
Author(s):  
Nam Hee Kim ◽  
Beom Jun Kim ◽  
Yeongun Ko ◽  
Jeong Ho Cho ◽  
Suk Tai Chang

ACS Omega ◽  
2021 ◽  
Author(s):  
Ryosuke Nitta ◽  
Ryo Taguchi ◽  
Yuta Kubota ◽  
Tetsuo Kishi ◽  
Atsushi Shishido ◽  
...  

2021 ◽  
Author(s):  
Nila Pal ◽  
Utkarsh Pandey ◽  
Sajal Biring ◽  
Bhola Nath Pal

Abstract A solution processed top-contact bottom gated SnO2 thin-film transistor (TFT) has been fabricated by using a TiO2/ Li-Al2O3 bilayer stacked gate dielectric that show operating voltage of this TFT within 2.0 V. It is observed that the bilayer dielectric has much higher areal capacitance with lower leakage current density that significantly improve the overall device performance of TFT. The TFT with bilayer gate dielectric shows an effective carrier mobility (µsat) of 9.2 cm2V− 1s− 1 with an on/off ratio of 7.1x103 which are significantly higher with respect to the TFT with a single layer Li-Al2O3 gate dielectric. The origin of this improvement is due to the Schottky junction between the highly doped silicon (p++-Si) and TiO2 of bilayer stacked dielectric that induced electrons to the channel which reduces the dielectric/semiconductor interface trap state. This investigation opens a new path to develop TFT device performance using a suitable bilayer stack of gate-dielectric.


2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Binghao Wang ◽  
Wei Huang ◽  
Sunghoon Lee ◽  
Lizhen Huang ◽  
Zhi Wang ◽  
...  

AbstractSolution processability of polymer semiconductors becomes an unfavorable factor during the fabrication of pixelated films since the underlying layer is vulnerable to subsequent solvent exposure. A foundry-compatible patterning process must meet requirements including high-throughput and high-resolution patternability, broad generality, ambient processability, environmentally benign solvents, and, minimal device performance degradation. However, known methodologies can only meet very few of these requirements. Here, a facile photolithographic approach is demonstrated for foundry-compatible high-resolution patterning of known p- and n-type semiconducting polymers. This process involves crosslinking a vertically phase-separated blend of the semiconducting polymer and a UV photocurable additive, and enables ambient processable photopatterning at resolutions as high as 0.5 μm in only three steps with environmentally benign solvents. The patterned semiconducting films can be integrated into thin-film transistors having excellent transport characteristics, low off-currents, and high thermal (up to 175 °C) and chemical (24 h immersion in chloroform) stability. Moreover, these patterned organic structures can also be integrated on 1.5 μm-thick parylene substrates to yield highly flexible (1 mm radius) and mechanically robust (5,000 bending cycles) thin-film transistors.


Sign in / Sign up

Export Citation Format

Share Document