Xtreme Low Power Technlogy Development Using a Virtual Design Flow: Enabling Technologies for AmbientIntelligence Applications

2006 ◽  
pp. 245-261 ◽  
Author(s):  
P. Christie ◽  
R.K.M. Ng ◽  
G. Doornbos ◽  
A. Heringa ◽  
A. Kumar ◽  
...  
Keyword(s):  
Low Power ◽  
Design Flow ◽  
Virtual Design ◽  
Enabling Technologies

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Low Power Wide Area Networks: A Survey of Enabling Technologies, Applications and Interoperability Needs

IEEE Access ◽  
2018 ◽  
Vol 6 ◽  
pp. 77454-77473 ◽  
Author(s):  
Qahhar Muhammad Qadir ◽  
Tarik A. Rashid ◽  
Nawzad K. Al-Salihi ◽  
Birzo Ismael ◽  
Alexander A. Kist ◽  
...  
Keyword(s):  
Low Power ◽  
Wide Area ◽  
Wide Area Networks ◽  
Enabling Technologies

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

Synopsys Low-Power Design Flow

2005 ◽  
pp. 1-20
Author(s):  
Renu Mehra ◽  
Barry Pangrle
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Flow

scholarly journals IEEE 802.15.4 and ZigBee as Enabling Technologies for Low-Power Wireless Systems with Quality-of-Service Constraints

2013 ◽  
Author(s):  
Stefano Tennina ◽  
Anis Koubâa ◽  
Roberta Daidone ◽  
Mário Alves ◽  
Petr Jurčík ◽  
...  
Keyword(s):  
Quality Of Service ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Wireless Systems ◽  
Enabling Technologies ◽  
Service Constraints

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

A Flexible Design Flow for a Low Power RFID Tag

2007 ◽  
Author(s):  
Jose C. S. Palma ◽  
Cesar Marcon ◽  
Fabiano Hessel ◽  
Eduardo Bezerra ◽  
Guilherme Rohde ◽  
...  
Keyword(s):  
Low Power ◽  
Design Flow ◽  
Flexible Design ◽  
Rfid Tag

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals Low Power Decoding of LDPC Codes

2013 ◽  
Vol 2013 ◽  
pp. 1-12 ◽  
Author(s):  
Mohamed Ismail ◽  
Imran Ahmed ◽  
Justin Coon
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Efficient Solutions ◽  
Design Flow ◽  
Wireless Sensor ◽  
Battery Life ◽  
Ldpc Decoding

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

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