Side-Channel Resistant Circuit Styles and Associated IC Design Flow

Abstract Just as we transitioned from simplistic lead frames to large ball grid arrays decades ago, we find ourselves again at another inflection point in design. Originally a derivative of PCB design, IC package design finds itself straddling both PCB-style design and traditional IC design. Dimensions have shrunk to place IC package design squarely in the same design dimensions as integrated circuits. Likewise, with Moore's law rapidly losing steam to support SoC's as a system integration vehicle, advanced package technologies have been asked to fill the system enablement gap. We now see advanced packaging technologies with silicon content as the system enabler in 2.5D, 3D and fanout wafer-level packaging. Because of the silicon and small geometries, IC design flows and signoff mechanisms are being used to design the next-generation of packaged systems. Package design now finds itself in the forefront of system-level design enablement. Where once system aggregation was done in a SoC at the silicon level, packaging is being used to build a system from technology-optimized die from each functional area (memory, processing, and interfaces). Silicon is no longer just a substrate material for IC manufacturing but a “package” substrate and functional integration vehicle. As such, package design teams find themselves adding IC-based design flows and methodologies. Package designers must look to the IC tools for routing, DRC, and signoff capabilities. Designers are looking for next-generation EDA tools to support these new integration and design challenges, including LVS-like validation checks and IC-based design rules. Rather than transitioning the design team from traditional packaging tools to IC tools entirely, we propose that users can leverage complete design flows that merge the best-in-class capabilities from each of their respective design domains. Is this regard, the best-in-class capabilities can remain in their respective domains, and a design flow can be created that relies on tight integration between both domains. These flows can also leverage a single point of entry for design capture and system level management. Flows based on the system management tool and the appropriate features in each of the domains can be created that enable and optimize complex designs that meet physical, signal integrity, cost and performance requirements. We will describe how capabilities can be leveraged from both domains in a tightly coupled flow, overseen by a design system-management tool, to address the challenges of advanced-technology and silicon-based system.

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A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

10.1109/date.2005.44 ◽

2005 ◽

Cited By ~ 44

Author(s):

K. Tiri ◽

I. Verbauwhede

Keyword(s):

Vlsi Design ◽

Design Flow ◽

Side Channel ◽

Side Channel Attack

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Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF

10.32920/ryerson.14664729.v1 ◽

2021 ◽

Author(s):

Charles Lim

Keyword(s):

Integrated Circuit ◽

Design Flow ◽

Ic Design ◽

Integrated Circuit Design ◽

Design Synthesis ◽

Radio Signals ◽

Hardware Description ◽

Communications Services ◽

Digital Predistorter ◽

Proper Operation

Radio over fiber has become one of the most useful technologies for providing extended coverage of wireless communications services. ROF uses analog fiber optic links to distribute wireless radio signals from a central location to multiple remote locations where the added desired antennas are placed for stronger signal coverage. The adaptive predistortion technique of a LASER ROF chip is implemented using the digital IC design flow. The design flow can be separated into two main parts, namely the RTL design / synthesis and the generation of the actual chip. The first part in the design flow consists of generating the proper logical functionality of the IC using a hardware description language (HDL), namely VHDL or Verilog, and synthesizing the code to ensure proper operation. The second part in the design flow consists of floorplanning and physical layout of the ASIC.

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Side-channel resistant system-level design flow for public-key cryptography

Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 ◽

10.1145/1228784.1228822 ◽

2007 ◽

Author(s):

Kazuo Sakiyama ◽

Elke De Mulder ◽

Bart Preneel ◽

Ingrid Verbauwhede

Keyword(s):

Public Key Cryptography ◽

Design Flow ◽

Public Key ◽

System Level ◽

Side Channel ◽

System Level Design ◽

Level Design

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Towards Efficient and Automated Side Channel Evaluations at Design Time

10.29007/mbf3 ◽

2018 ◽

Author(s):

Danilo Šijačić ◽

Josep Balasch ◽

Bohan Yang ◽

Santosh Ghosh ◽

Ingrid Verbauwhede

Keyword(s):

Experimental Validation ◽

State Of The Art ◽

Information Leakage ◽

Design Flow ◽

Side Channel ◽

Cell Design ◽

Standard Cell ◽

Side Channel Analysis ◽

Design Time ◽

Channel Analysis

Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate and easily automated pre-silicon estimates for e.g. timing and area figures. In this work we design, implement, and evaluate CASCADE, a framework that combines a largely automated full-stack standard-cell design flow with the state of the art techniques for side channel analysis. We show how it can be used to efficiently evaluate side channel leakage prior to chip manufacturing. Moreover, it is independent of the underlying countermeasure and it can be applied starting from the earliest stages of the design flow. Additionally, we provide experimental validation through assessment of the side channel security of representative cryptographic circuits. We discuss aspects related to the performance, scalability, and utility to the designers. In particular, we show that CASCADE can evaluate information leakage with 1 million simulated traces in less than 4 hours using a single desktop workstation, for a design larger than 100kGE.

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