Above 160 dB Dynamic-Range Gas-Sensor-Grid Front-end Integrated Circuit with 500 °C, 1.5 °C/Pitch Temperature Gradient Synthesis, 20-Channel MUX, and I2C Interface

2015 ◽  
pp. 297-301
Author(s):  
F. Conso ◽  
M. Grassi ◽  
C. De Berti ◽  
P. Malcovati ◽  
A. Baschirotto
Keyword(s):  
Temperature Gradient ◽  
Gas Sensor ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Front End

scholarly journals Design and Optimization of a Direct-Conversion Double-Balanced Mixer for RF Receiver Front-End

2018 ◽  
Vol 1 (3) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Radio Frequency ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Noise Figure ◽  
Past Research ◽  
Direct Conversion ◽  
Oxide Semiconductor ◽  
Front End ◽  
Mixer Design ◽  
Balanced Mixer

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer.  This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process.  Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver.   Impedance matching was essential to fully optimize the mixer design.  The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.

scholarly journals ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2074
Author(s):  
Evgenia Voulgari ◽  
François Krummenacher ◽  
Maher Kayal
Keyword(s):  
Integrated Circuit ◽  
Energy Efficient ◽  
Dynamic Range ◽  
Field Effect Transistors ◽  
Frequency Converter ◽  
Sensor Data ◽  
Current Sensing ◽  
Analog To Digital ◽  
Sensing System ◽  
Front End

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically designed to interface with multiple Ion-Sensitive Field-Effect Transistors (ISFETs) and detect biomarkers like pH, Na+, K+ and Ca2+ in human sweat. The ISFET-ASIC system can allow real-time noninvasive and continuous health monitoring. The ANTIGONE ASIC architecture is based on the current-to-frequency converter through the charge balancing principle. The same front-end can digitize multiple currents produced by four sweat ISFET sensors in time multiplexing. The front-end demonstrates good linearity over a dynamic range that spans from 1 pA up to 500 nA. The consumed energy per conversion is less than 1 J. The chip is programmable and works in eight different modes of operation. The system uses a standard Serial Peripheral Interface (SPI) to configure, control and read the digitally converted sensor data. The chip is controlled by a portable device over Bluetooth Low Energy (BLE) through a Microcontroller Unit (MCU). The sweat sensing system is part of a bigger wearable platform that exploits the convergence of multiparameter biosensors and environmental sensors for personalized and preventive healthcare.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

A Floating-Gate-Based Four-Channel Reconfigurable Analog Front-End Integrated Circuit

2021 ◽  
Author(s):  
Zu-Jia Lo ◽  
Bipasha Nath ◽  
Yuan-Chuan Wang ◽  
Yun-Jie Huang ◽  
Hui-Chun Huang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Floating Gate ◽  
Front End ◽  
Analog Front End

An analog BiCMOS integrated circuit for front-end RDS decoder

1991 ◽  
Vol 37 (3) ◽  
pp. 585-591 ◽  
Author(s):  
A. Baschirotto ◽  
M. Cassis ◽  
P. Kirchlechner ◽  
F. Montecchi ◽  
G. Palmisano ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Front End

Analog Integrated Circuit for Edge Detection with wide Dynamic Range Based on Vertebrate Outer Retina

2006 ◽  
Vol 12 (3) ◽  
pp. 299-305 ◽  
Author(s):  
Shinya Sawa ◽  
Kimihiro Nishio ◽  
Yuzo Furukawa ◽  
Hiroo Yonezu ◽  
Jang-Kyoo Shin
Keyword(s):  
Edge Detection ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Outer Retina ◽  
Wide Dynamic Range ◽  
Analog Integrated Circuit

scholarly journals A 2-bit, 3.1 GS/s, band-pass DSM receiver for active antenna systems

2013 ◽  
Vol 5 (3) ◽  
pp. 329-334 ◽  
Author(s):  
Udo Karthaus ◽  
Stephan Ahles ◽  
Ahmed Elmaghraby ◽  
Horst Wagner
Keyword(s):  
Integrated Circuit ◽  
Dynamic Range ◽  
Noise Figure ◽  
Base Stations ◽  
Active Antenna ◽  
Single Carrier ◽  
Bicmos Technology ◽  
Band Pass ◽  
Time Band ◽  
Antenna Systems

This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are −6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is −62.6 and −52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier.

Unified and Integrated Circuit Antenna in Front End—A Proof of Concept

2019 ◽  
Vol 67 (1) ◽  
pp. 347-364 ◽  
Author(s):  
Srinaga Nikhil Nallandhigal ◽  
Ke Wu
Keyword(s):  
Integrated Circuit ◽  
Proof Of Concept ◽  
Front End
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