scholarly journals ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2074
Author(s):  
Evgenia Voulgari ◽  
François Krummenacher ◽  
Maher Kayal
Keyword(s):  
Integrated Circuit ◽  
Energy Efficient ◽  
Dynamic Range ◽  
Field Effect Transistors ◽  
Frequency Converter ◽  
Sensor Data ◽  
Current Sensing ◽  
Analog To Digital ◽  
Sensing System ◽  
Front End

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically designed to interface with multiple Ion-Sensitive Field-Effect Transistors (ISFETs) and detect biomarkers like pH, Na+, K+ and Ca2+ in human sweat. The ISFET-ASIC system can allow real-time noninvasive and continuous health monitoring. The ANTIGONE ASIC architecture is based on the current-to-frequency converter through the charge balancing principle. The same front-end can digitize multiple currents produced by four sweat ISFET sensors in time multiplexing. The front-end demonstrates good linearity over a dynamic range that spans from 1 pA up to 500 nA. The consumed energy per conversion is less than 1 J. The chip is programmable and works in eight different modes of operation. The system uses a standard Serial Peripheral Interface (SPI) to configure, control and read the digitally converted sensor data. The chip is controlled by a portable device over Bluetooth Low Energy (BLE) through a Microcontroller Unit (MCU). The sweat sensing system is part of a bigger wearable platform that exploits the convergence of multiparameter biosensors and environmental sensors for personalized and preventive healthcare.

scholarly journals One-chip analog circuits for a new type of plasma wave receiver on board space missions

2017 ◽  
Vol 6 (1) ◽  
pp. 159-167 ◽  
Author(s):  
Takahiro Zushi ◽  
Hirotsugu Kojima ◽  
Hiroshi Yamakawa
Keyword(s):  
Plasma Wave ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Test System ◽  
Analog To Digital ◽  
Application Specific Integrated Circuit ◽  
New Type ◽  
Narrow Dynamic Range ◽  
Asic Chip

Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm  ×  1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

GAS SENSING SYSTEM CONSISTING IN MOX-BASED MICROSENSORS INTERFACED TO A NOVEL INTEGRATED 5-DECADE DYNAMIC RANGE FRONT-END

2008 ◽  
Author(s):  
Marco Grassi ◽  
Piero Malcovati ◽  
Simonetta Capone ◽  
Luca Francioso ◽  
Pietro Siciliano ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Gas Sensing ◽  
Sensing System ◽  
Front End

scholarly journals One-chip analogue circuits for a new type of plasma wave receiver onboard space missions

2016 ◽  
Author(s):  
Takahiro Zushi ◽  
Hirotsugu Kojima ◽  
Hiroshi Yamakawa
Keyword(s):  
Plasma Wave ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Test System ◽  
Analog To Digital ◽  
Analogue Circuits ◽  
Application Specific Integrated Circuit ◽  
New Type ◽  
Asic Chip

Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm x 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

scholarly journals VMM - An ASIC for Micropattern Detectors

2018 ◽  
Vol 174 ◽  
pp. 07001 ◽  
Author(s):  
George Iakovidis
Keyword(s):  
Integrated Circuit ◽  
National Laboratory ◽  
Ball Grid Array ◽  
Brookhaven National Laboratory ◽  
Analog To Digital ◽  
Front End ◽  
Wide Range ◽  
Multiplexed Readout ◽  
Application Specific Integrated Circuit ◽  
Application Specific

The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

scholarly journals Design and Optimization of a Direct-Conversion Double-Balanced Mixer for RF Receiver Front-End

2018 ◽  
Vol 1 (3) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Radio Frequency ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Noise Figure ◽  
Past Research ◽  
Direct Conversion ◽  
Oxide Semiconductor ◽  
Front End ◽  
Mixer Design ◽  
Balanced Mixer

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer.  This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process.  Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver.   Impedance matching was essential to fully optimize the mixer design.  The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.

Advanced Analog-to-Digital Conversion Using Voltage-to-Frequency Converters for Remote Sensors

2008 ◽  
Vol 381-382 ◽  
pp. 623-626 ◽  
Author(s):  
Sergey Y. Yurish
Keyword(s):  
High Performance ◽  
Frequency Conversion ◽  
Dynamic Range ◽  
Low Cost ◽  
Frequency Converter ◽  
Charge Balance ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Remote Sensors ◽  
Analog To Digital Conversion

This paper presents an advanced analog-to-digital conversion technique based on a voltage-to-frequency-to-digital conversion that is suitable for remote sensors, telemetry applications and multichannel data acquisition systems. A voltage-to-frequency conversion part can be based, for example, on high performance, charge-balance voltage-to-frequency converter (VFC), where monostable is replaced by a bistable, driven by an external clock, or other existing high performance VFCs. The frequency-to-digital converter “bottleneck” problem in such promised ADC scheme was solved due to proposed advanced method of the dependent count for frequency-to-digital conversion. This ADC technique lets receive many advantages such as high accuracy, relatively low power consumption, low cost solution, wide dynamic range, great stability and faster conversion time in comparison with existing VFC-based techniques. The conversion rate (6.25 µs to 6.25 ms) in such ADC scheme is programmable, non-redundant, shorter than for pulse counting technique and comparable with successive-approximation and Σ- ADC.

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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