LED Die Bonding

2016 ◽  
pp. 733-766
Author(s):  
Yu-Chou Shih ◽  
Gunwoo Kim ◽  
Jiun-Pyng You ◽  
Frank G. Shi
Keyword(s):  
Author(s):  
Jinglong Li ◽  
Motohiko Masuda ◽  
Yi Che ◽  
Miao Wu

Abstract Die attach is well known in die bonding process. Its electrical character is simple. But some failures caused by die attach are not so simple. And it is not proper to analyze by a generic analysis flow. The analysis of two failures caused by die attach are presented in this paper.


Author(s):  
Shingo Ishihara ◽  
Tetsu Takemasa ◽  
Katsuaki Suganuma ◽  
Junya Kano

2006 ◽  
Vol 527-529 ◽  
pp. 875-878 ◽  
Author(s):  
Seung Yong Lee ◽  
Jang Sub Lee ◽  
Tae Hong Kim ◽  
Sung Yong Choi ◽  
Hak Jong Kim ◽  
...  

We report on the die bonding processes and how the surface roughness and metallization schemes affect the processes of die bonding in 4H-SiC device fabrication using a soldering test and die shear test (DST) with differently prepared 4H-SiC samples. The first set of samples (FZ#1 and FZ#2) was capped with sequentially evaporated Ti and Au on an annealed Ni layer. The second set of samples (FZ#3 and FZ#4) and the third set of samples (FZ#5 and FZ#6) were prepared by 4μm-thick Au electroplating on an annealed Ni layer and an un-annealed Ni layer, respectively. The quality of the soldering, such as the solder coverage, void, and adhesion, was characterized by optical microscope, X-ray microprobe, and DST. We found that the samples (FZ#4 and FZ#6) deposited by Au electroplating on C-face (bottom-side) 4H-SiC provided a satisfactory result for the tests of solder coverage, void, and DST and also realized the cleaning process prior to the electroplating and soldering was the most crucial in the die packaging processes of vertical structure devices. The void fraction measured by X-ray microprobe for the samples, FZ#4 and FZ#6 was 2.2% (average for 5 samples) and 0.8% (average for 3 samples), respectively.


2014 ◽  
Vol 43 (12) ◽  
pp. 4510-4514 ◽  
Author(s):  
V. Caccuri ◽  
X. Milhet ◽  
P. Gadaud ◽  
D. Bertheau ◽  
M. Gerland

Author(s):  
A. De Groote ◽  
J. D. Peters ◽  
M. L. Davenport ◽  
M. J. R. Heck ◽  
R. Baets ◽  
...  

2016 ◽  
Vol 55 (4S) ◽  
pp. 04EC14 ◽  
Author(s):  
Masahisa Fujino ◽  
Hirozumi Narusawa ◽  
Yuzuru Kuramochi ◽  
Eiji Higurashi ◽  
Tadatomo Suga ◽  
...  

Author(s):  
Seung Yong Lee ◽  
Jang Sub Lee ◽  
Tae Hong Kim ◽  
Sung Yong Choi ◽  
Hak Jong Kim ◽  
...  
Keyword(s):  

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch


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