Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory

2004 ◽  
pp. 88-101
Author(s):  
Ying Chen ◽  
Karthik Ranganathan ◽  
Vasudev V. Pai ◽  
David J. Lilja ◽  
Kia Bazargan
Keyword(s):  
Embedded Systems ◽  
Memory Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Solution-processable black phosphorus nanosheets covalently modified with polyacrylonitrile for nonvolatile resistive random access memory

2020 ◽  
Vol 8 (4) ◽  
pp. 1231-1238
Author(s):  
Minchao Gu ◽  
Bin Zhang ◽  
Bo Liu ◽  
Qiang Che ◽  
Zhizheng Zhao ◽  
...  
Keyword(s):  
Memory Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Black Phosphorus ◽  
Access Memory ◽  
Current Ratio ◽  
Solution Processable

The as-fabricated Al/BP–PAN/ITO device exhibits excellent nonvolatile rewritable memory performance, with a high ON/OFF current ratio exceeding 104 and a small switch-on voltage of −1.45 V.

scholarly journals Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 952
Author(s):  
Songyi Yoo ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Retention Time ◽  
Computer Aided Design ◽  
Memory Performance ◽  
Scaling Limit ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Aided Design

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

scholarly journals Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1209
Author(s):  
Yejin Ha ◽  
Hyungsoon Shin ◽  
Wookyung Sun ◽  
Jisun Park
Keyword(s):  
Memory Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Optimization Method ◽  
Memory Device ◽  
Circuit Optimization ◽  
Access Memory ◽  
Source Line ◽  
Bias Condition ◽  
Circuit Configuration

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems

2014 ◽  
Vol 10 (3) ◽  
pp. 467-478
Author(s):  
Luo Sun ◽  
J. Mathew ◽  
S. Pagliarini ◽  
Dhiraj K. Pradhan ◽  
Ioannis Sourdis
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
Binary Tree ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

2005 ◽  
Vol 20 (5) ◽  
pp. 596-606
Author(s):  
Ying Chen ◽  
Karthik Ranganathan ◽  
Vasudev V. Pai ◽  
David J. Lilja ◽  
Kia Bazargan
Keyword(s):  
Embedded Systems ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Structure ◽  
Access Memory

Basic Issues

2004 ◽  
Author(s):  
Wesley Petersen ◽  
Peter Arbenz
Keyword(s):  
Memory Performance ◽  
Direct Memory Access ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Systems ◽  
Close Packing ◽  
Memory Access ◽  
Processing Unit ◽  
Access Memory ◽  
Central Processing

Since first proposed by Gordon Moore (an Intel founder) in 1965, his law [107] that the number of transistors on microprocessors doubles roughly every one to two years has proven remarkably astute. Its corollary, that central processing unit (CPU) performance would also double every two years or so has also remained prescient. Figure 1.1 shows Intel microprocessor data on the number of transistors beginning with the 4004 in 1972. Figure 1.2 indicates that when one includes multi-processor machines and algorithmic development, computer performance is actually better than Moore’s 2-year performance doubling time estimate. Alas, however, in recent years there has developed a disagreeable mismatch between CPU and memory performance: CPUs now outperform memory systems by orders of magnitude according to some reckoning [71]. This is not completely accurate, of course: it is mostly a matter of cost. In the 1980s and 1990s, Cray Research Y-MP series machines had well balanced CPU to memory performance. Likewise, NEC (Nippon Electric Corp.), using CMOS (see glossary, Appendix F) and direct memory access, has well balanced CPU/Memory performance. ECL (see glossary, Appendix F) and CMOS static random access memory (SRAM) systems were and remain expensive and like their CPU counterparts have to be carefully kept cool. Worse, because they have to be cooled, close packing is difficult and such systems tend to have small storage per volume. Almost any personal computer (PC) these days has a much larger memory than supercomputer memory systems of the 1980s or early 1990s. In consequence, nearly all memory systems these days are hierarchical, frequently with multiple levels of cache. Figure 1.3 shows the diverging trends between CPUs and memory performance. Dynamic random access memory (DRAM) in some variety has become standard for bulk memory. There are many projects and ideas about how to close this performance gap, for example, the IRAM [78] and RDRAM projects [85]. We are confident that this disparity between CPU and memory access performance will eventually be tightened, but in the meantime, we must deal with the world as it is.

scholarly journals A system verilog approach for verification of memory controller

2020 ◽  
Vol 9 (2) ◽  
pp. 153
Author(s):  
Sowmya K B ◽  
Gagana P
Keyword(s):  
Memory Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Design Flow ◽  
Effective Control ◽  
Access Memory ◽  
Memory Controller ◽  
Major Bottleneck ◽  
Overall Performance ◽  
Read Only Memory

<span>Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.</span>

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