A NOVEL ADIABATIC REGISTER FILE DESIGN

2000 ◽  
Vol 10 (01n02) ◽  
pp. 67-76 ◽  
Author(s):  
K. W. NG ◽  
K. T. LAU
Keyword(s):  
Power Consumption ◽  
Register File ◽  
Adiabatic Switching ◽  
Adiabatic Logic ◽  
File Design ◽  
Pass Transistor ◽  
Simulation Results ◽  
Cmos Implementation ◽  
Large Capacitance ◽  
Hspice Simulation

A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Full Adder ◽  
Double Pass ◽  
Voltage Level ◽  
Circuit Performance ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Implementation ◽  
Low Power Multiplier

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

Design of low power and high speed implicit pulse flip-flop and its application

2018 ◽  
Vol 7 (3) ◽  
pp. 1893 ◽  
Author(s):  
Kuruvilla John ◽  
Vinod Kumar R S ◽  
Kumar S S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Product Performance ◽  
Power Performance ◽  
Flip Flop ◽  
Power Efficient ◽  
Pass Transistor ◽  
Simulation Results ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.  

Design of Dynamic Binary Circuits Based on Floating-Gate Technology

2013 ◽  
Vol 347-350 ◽  
pp. 1323-1327
Author(s):  
Xiao Hui Hu ◽  
Guo Qiang Hang ◽  
Yang Yang ◽  
Xiao Hu You
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Floating Gate ◽  
Circuit Structure ◽  
Simulation Results ◽  
Circuit Technology ◽  
Hspice Simulation

The dynamic circuit technology can decrease the whole power consumption, and the Floating-gate technology can simplify the circuit structure, which will also decrease the area and power consumption of IC. Taking the advantages of both ,we propose a new dynamic binary circuit based on floating-gate technology. The HSPICE simulation results using TSMC 0.35μm double-polysilicon CMOS technology validate the correctness of the proposed approach, and the proposed circuits also have considerable simpler structures.

Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques

2010 ◽  
Vol 39 ◽  
pp. 55-60 ◽  
Author(s):  
Bin Bin Lu ◽  
Jian Ping Hu
Keyword(s):  
Energy Dissipation ◽  
Full Adder ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Simulation Results ◽  
Scaling Down

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

2010 ◽  
Vol 159 ◽  
pp. 155-161
Author(s):  
Jin Tao Jiang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Gate Structure ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
P Type ◽  
Cmos Processes

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 97-102 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Li Su ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Power Dissipation ◽  
Low Power Design ◽  
Logic Circuits ◽  
Leakage Power ◽  
Nanometer Cmos ◽  
Wide Range ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor ◽  
Simulation Results

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

scholarly journals Performance Evaluation of an Efficient 5-2 Compressor for Digital Applications

2019 ◽  
Vol 9 (1) ◽  
pp. 5307-5310
Keyword(s):  
Performance Evaluation ◽  
Power Consumption ◽  
Full Adder ◽  
Efficient Performance ◽  
Pass Transistor ◽  
Overall Performance ◽  
Simulation Results ◽  
Pass Transistor Logic ◽  
Power Delay Product

This paper presents an efficient performance 5-2 compressor which consumes less power. The architecture of this compressor consists of full adder, XOR’s, CGEN and MUX blocks. This architecture is mainly implemented based on Cout signals independent of Cin signals in order to reduce the carry propagation to a compressor. An efficient full adder is used to optimize the compressor architecture. In this design, an existing carry generator, XOR, MUX blocks configure with the proposed full adder circuit. The proposed design for full adder employs using pass transistor logic, which eliminates the weak logic in the circuit. This technique is mainly considerable for less power consumption. The parameters of proposed architecture is compared with other designs i.e. power-delay product, averagepower, and delay. Simulations were done using HSPICE software in 130nm and 32nm technology. The simulation results show the improvement in the overall performance of the 5-2 compressor.

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