Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach

2011 ◽  
Vol 27 (6) ◽  
pp. 711-721 ◽  
Author(s):  
Chunhua Yao ◽  
Kewal K. Saluja ◽  
Parmesh Ramanathan
Keyword(s):  
Integrated Circuits ◽  
Thermal Sensors ◽  
On Chip ◽  
Calibration Approach

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

scholarly journals Interband Cascade Photonic Integrated Circuits on Native III-V Chip

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 599
Author(s):  
Jerry R. Meyer ◽  
Chul Soo Kim ◽  
Mijin Kim ◽  
Chadwick L. Canedy ◽  
Charles D. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Laser Cavity ◽  
Building Blocks ◽  
Drive Power ◽  
Optical Elements ◽  
Photonic Integrated Circuit ◽  
Cleaved Facets ◽  
On Chip

We describe how a midwave infrared photonic integrated circuit (PIC) that combines lasers, detectors, passive waveguides, and other optical elements may be constructed on the native GaSb substrate of an interband cascade laser (ICL) structure. The active and passive building blocks may be used, for example, to fabricate an on-chip chemical detection system with a passive sensing waveguide that evanescently couples to an ambient sample gas. A variety of highly compact architectures are described, some of which incorporate both the sensing waveguide and detector into a laser cavity defined by two high-reflectivity cleaved facets. We also describe an edge-emitting laser configuration that optimizes stability by minimizing parasitic feedback from external optical elements, and which can potentially operate with lower drive power than any mid-IR laser now available. While ICL-based PICs processed on GaSb serve to illustrate the various configurations, many of the proposed concepts apply equally to quantum-cascade-laser (QCL)-based PICs processed on InP, and PICs that integrate III-V lasers and detectors on silicon. With mature processing, it should become possible to mass-produce hundreds of individual PICs on the same chip which, when singulated, will realize chemical sensing by an extremely compact and inexpensive package.

High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor

2019 ◽  
Vol 963 ◽  
pp. 832-836 ◽  
Author(s):  
Shuo Ben Hou ◽  
Per Erik Hellström ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Room Temperature ◽  
Uv Light ◽  
Optical Power ◽  
Current Gain ◽  
High Current ◽  
Promising Candidate ◽  
Forward Current ◽  
On Chip

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 °C. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 °C. βFmax drops to 51 at 400 °C and remains the same at 500 °C. The photocurrent gain of the phototransistor is 3.9 at 25 °C and increases to 14 at 500 °C under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4H-SiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics on-chip integration.

A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications

2007 ◽  
Vol 4 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Qing Liu ◽  
Patrick Fay ◽  
Gary H. Bernstein
Keyword(s):  
Integrated Circuits ◽  
Coplanar Waveguide ◽  
Impedance Matching ◽  
Three Dimensional ◽  
Fabrication Process ◽  
Silicon Substrates ◽  
Electromagnetic Simulations ◽  
Communication Paradigm ◽  
On Chip ◽  
Test Chips

Quilt Packaging (QP), a novel chip-to-chip communication paradigm for system-in-package integration, is presented. By forming protruding metal nodules along the edges of the chips and interconnecting integrated circuits (ICs) through them, QP offers an approach to ameliorate the I/O speed bottleneck. A fabrication process that includes deep reactive ion etching, electroplating, and chemical-mechanical polishing is demonstrated. As a low-temperature process, it can be easily integrated into a standard IC fabrication process. Three-dimensional electromagnetic simulations of coplanar waveguide QP structures have been performed, and geometries intended to improve impedance matching at the interface between the on-chip interconnects and the chip-to-chip nodule structures were evaluated. Test chips with 100 μm wide nodules were fabricated on silicon substrates, and s-parameters of chip-to-chip interconnects were measured. The insertion loss of the chip-to-chip interconnects was as low as 0.2 dB at 40 GHz. Simulations of 20 μm wide QP structures suggest that the bandwidth of the inter-chip nodules is expected to be above 200 GHz.

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