A full adder structure with a unique XNOR gate based on Coulomb interaction in QCA nanotechnology

2021 ◽  
Vol 53 (8) ◽  
Author(s):  
Fereshteh Salimzadeh ◽  
Saeed Rasouli Heikalabad
Keyword(s):  
Coulomb Interaction ◽  
Full Adder ◽  
Xnor Gate

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

2016 ◽  
Vol 5 (03) ◽  
pp. 07-12
Author(s):  
Prof. Amruta Bijwar
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Full Adder ◽  
Basic Component ◽  
Xnor Gate ◽  
Transmission Gates ◽  
Design Systems ◽  
Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

scholarly journals Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

2021 ◽  
Vol 12 (3) ◽  
pp. 5720-5725
Author(s):  
A.S Keerthi Nayani Et. al.
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Ripple Carry Adder ◽  
Xnor Gate ◽  
Low Power Cmos

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

scholarly journals Design of Low Power Adder Cell by XOR & XNOR Gate

2020 ◽  
Vol 9 (1) ◽  
pp. 2560-2564
Keyword(s):  
Full Adder ◽  
Hybrid Technique ◽  
Low Leakage ◽  
Research Article ◽  
Xnor Gate ◽  
Reference Design ◽  
Previous Design ◽  
Dissipation Power ◽  
Exclusive Or ◽  
Or Gate

In under this research article, neoteric circuits for Exclusive OR gate and Exclusive NOR gate are designed. The designed logic is highly refined in terms of power consummation and speed, which are due to minimum CL at the output and low leakage power. We followed six novel hybrids, one bit one full-adder design based on the new Exclusive OR gate and Exclusive NOR (XOR-XNOR) gates. Many Relevant designed logics carries its advantages within aspect relevant to delay power, dissipation power, speed, as well as all that. Within validate the presentation of the introduced design, major SPICE as well as Tanner EDA simulations function as executed. This simulation outcomes, arrange at a 65-nanometer based on hybrid technique process, reveal for the introduced architecture have the best speed and power in contempt of different Full Adder architectures. The proposed design has a minimum power of 0.8 nw & delay of 9.4 ns, which is very optimized & efficient than the reference design. The previous design has 4.08-microwatt power. We customized the design with 22T and change the design methodology to make the results optimized.

Nanotechnology (45 nm) based Low power and High performance 4x4 Multiplier based on Six Transistors (6T) Full Adder & 2T XNOR Gate

2021 ◽  
Author(s):  
Misha Urooj Khan ◽  
Muhammad Zeeshan ◽  
Usama Gulzar ◽  
Muhammad Muneeb ◽  
Zeeshan Abbasi ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Xnor Gate
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