Speeding up carbon nanotube integrated circuits through three-dimensional architecture

Nano Research ◽  
2019 ◽  
Vol 12 (8) ◽  
pp. 1810-1816 ◽  
Author(s):  
Yunong Xie ◽  
Zhiyong Zhang ◽  
Donglai Zhong ◽  
Lianmao Peng
Keyword(s):  
Carbon Nanotube ◽  
Integrated Circuits ◽  
Three Dimensional

scholarly journals Simulation and fabrication of carbon nanotube–nanoparticle interconnected structures

2021 ◽  
Vol 12 (1) ◽  
pp. 451-459
Author(s):  
Xiwen Lu ◽  
Jinhang Liu ◽  
Ye Ding ◽  
Lijun Yang ◽  
Zhan Yang ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Carbon Nanotube ◽  
Integrated Circuits ◽  
Rapid Development ◽  
Three Dimensional ◽  
Silver Nanocluster ◽  
Nano Fabrication ◽  
3D Manipulation ◽  
Nano Structures ◽  
Silicon Based

Abstract. With the rapid development of nanotechnology, the size of a device reaches sub-nanometer scale. The larger resistivity of interconnect leads to serious overheating of integrated circuits. Silicon-based electronic devices have also reached the physical limits of their development. The use of carbon nanotubes instead of traditional wires has become a new solution for connecting nano-structures. Nanocluster particles serving as brazing material play an important role in stabilizing the connection of carbon nanotubes, which places higher demands for nanoscale manipulation techniques. In this paper, the dynamic processes under different operating scenarios were simulated and analyzed, including probe propulsion nanoparticle operation, probe pickup nanoparticle operation and probe pickup nanocluster particle operation. Then, the SEM (Scanning Electron Microscope) was used for nanoparticle manipulation experiments. The smallest unit of carbon nanotube wire was obtained by three-dimensional (3D) construction of a carbon nanotube–silver nanocluster particle (CN-AgNP), which verified the feasibility of 3D manipulation of carbon nanotube wire construction. The experiments on the construction of carbon nanotube–nanocluster particle structures in three-dimensional operation were completed, and the smallest unit of carbon nanotube wire was constructed. This nano-fabrication technology will provide an efficient and mature technical means in the field of nano-interconnection.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

Sign in / Sign up

Export Citation Format

Share Document