Propagation Delay and Timing Defects in Combinational Logic

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

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Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽

10.1557/s0883769400034151 ◽

1997 ◽

Vol 22 (10) ◽

pp. 19-27 ◽

Cited By ~ 86

Author(s):

Wei William Lee ◽

Paul S. Ho

Keyword(s):

Packing Density ◽

Propagation Delay ◽

Single Chip ◽

Crosstalk Noise ◽

Metal Line ◽

Total Delay ◽

Interlayer Dielectric ◽

Low Dielectric ◽

Interconnect Delay ◽

Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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Combinational Logic Analysis Using Laser Voltage Probing

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0035 ◽

2015 ◽

Author(s):

Venkat Krishnan Ravikumar ◽

Winson Lua ◽

Seah Yi Xuan ◽

Gopinath Ranganathan ◽

Angeline Phoa

Keyword(s):

Failure Analysis ◽

Continuous Wave ◽

Truth Table ◽

Combinational Logic ◽

Infra Red ◽

Analysis Design ◽

Logic State

Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

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Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

Current Signal Transduction Therapy ◽

10.2174/1574362414666191202100807 ◽

2019 ◽

Vol 14 ◽

Author(s):

Teresa V.V ◽

Anand. B

Keyword(s):

Research Work ◽

Low Complexity ◽

Propagation Delay ◽

Maximum Speed ◽

Hyper Spectral ◽

Ripple Carry Adder ◽

Minimum Power Consumption ◽

Carry Select Adder ◽

The Look ◽

Propagation Result

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

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A Concurrent BIST Architecture for Combinational Logic Circuits

2020 10th International Conference on Computer and Knowledge Engineering (ICCKE) ◽

10.1109/iccke50421.2020.9303669 ◽

2020 ◽

Author(s):

Ahmad Menbari ◽

Hadi Jahanirad

Keyword(s):

Logic Circuits ◽

Combinational Logic ◽

Combinational Logic Circuits

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Investigating Master–Slave Architecture for Underwater Wireless Sensor Network

Sensors ◽

10.3390/s21093000 ◽

2021 ◽

Vol 21 (9) ◽

pp. 3000

Author(s):

Sadeeq Jan ◽

Eiad Yafi ◽

Abdul Hafeez ◽

Hamza Waheed Khatana ◽

Sajid Hussain ◽

...

Keyword(s):

Wireless Sensor Network ◽

Sensor Network ◽

Propagation Delay ◽

Data Packet ◽

Wireless Sensor ◽

Delivery Ratio ◽

Term Survival ◽

Limited Bandwidth ◽

Delay Tolerant

A significant increase has been observed in the use of Underwater Wireless Sensor Networks (UWSNs) over the last few decades. However, there exist several associated challenges with UWSNs, mainly due to the nodes’ mobility, increased propagation delay, limited bandwidth, packet duplication, void holes, and Doppler/multi-path effects. To address these challenges, we propose a protocol named “An Efficient Routing Protocol based on Master–Slave Architecture for Underwater Wireless Sensor Network (ERPMSA-UWSN)” that significantly contributes to optimizing energy consumption and data packet’s long-term survival. We adopt an innovative approach based on the master–slave architecture, which results in limiting the forwarders of the data packet by restricting the transmission through master nodes only. In this protocol, we suppress nodes from data packet reception except the master nodes. We perform extensive simulation and demonstrate that our proposed protocol is delay-tolerant and energy-efficient. We achieve an improvement of 13% on energy tax and 4.8% on Packet Delivery Ratio (PDR), over the state-of-the-art protocol.

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Packet Flow Based Reinforcement Learning MAC Protocol for Underwater Acoustic Sensor Networks

Sensors ◽

10.3390/s21072284 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2284

Author(s):

Ibrahim B. Alhassan ◽

Paul D. Mitchell

Keyword(s):

Sensor Networks ◽

Mac Protocol ◽

Propagation Delay ◽

Basic Function ◽

Acoustic Sensor ◽

Underwater Acoustic Sensor Networks ◽

Medium Access ◽

Underwater Acoustic ◽

Q Learning ◽

Acoustic Sensor Networks

Medium access control (MAC) is one of the key requirements in underwater acoustic sensor networks (UASNs). For a MAC protocol to provide its basic function of efficient sharing of channel access, the highly dynamic underwater environment demands MAC protocols to be adaptive as well. Q-learning is one of the promising techniques employed in intelligent MAC protocol solutions, however, due to the long propagation delay, the performance of this approach is severely limited by reliance on an explicit reward signal to function. In this paper, we propose a restructured and a modified two stage Q-learning process to extract an implicit reward signal for a novel MAC protocol: Packet flow ALOHA with Q-learning (ALOHA-QUPAF). Based on a simulated pipeline monitoring chain network, results show that the protocol outperforms both ALOHA-Q and framed ALOHA by at least 13% and 148% in all simulated scenarios, respectively.

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Effective Data Transmission and Control Based on Social Communication in Social Opportunistic Complex Networks

Complexity ◽

10.1155/2020/3721579 ◽

2020 ◽

Vol 2020 ◽

pp. 1-20 ◽

Cited By ~ 3

Author(s):

Weiyu Yang ◽

Jia Wu ◽

Jingwen Luo

Keyword(s):

Complex Networks ◽

Information Transmission ◽

Interference Cancellation ◽

Propagation Delay ◽

Transmission Efficiency ◽

Successive Interference Cancellation ◽

Time Slice ◽

Signal Interference ◽

Time Signal ◽

Interference Avoidance

In opportunistic complex networks, information transmission between nodes is inevitable through broadcast. The purpose of broadcasting is to distribute data from source nodes to all nodes in the network. In opportunistic complex networks, it is mainly used for routing discovery and releasing important notifications. However, when a large number of nodes in the opportunistic complex networks are transmitting information at the same time, signal interference will inevitably occur. Therefore, we propose a low-latency broadcast algorithm for opportunistic complex networks based on successive interference cancellation techniques to improve propagation delay. With this kind of algorithm, when the social network is broadcasting, this algorithm analyzes whether the conditions for successive interference cancellation are satisfied between the broadcast links on the assigned transmission time slice. If the conditions are met, they are scheduled at the same time slice, and interference avoidance scheduling is performed when conditions are not met. Through comparison experiments with other classic algorithms of opportunistic complex networks, this method has outstanding performance in reducing energy consumption and improving information transmission efficiency.

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