Combinational Logic Analysis Using Laser Voltage Probing

2015 ◽  
Author(s):  
Venkat Krishnan Ravikumar ◽  
Winson Lua ◽  
Seah Yi Xuan ◽  
Gopinath Ranganathan ◽  
Angeline Phoa
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Truth Table ◽  
Combinational Logic ◽  
Infra Red ◽  
Analysis Design ◽  
Logic State

Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

scholarly journals Design of Combinational Logic Circuit Prober

2019 ◽  
Vol 24 (4) ◽  
pp. 317-325
Author(s):  
Mohanad Abdulhamid ◽  
Okoth Masimba
Keyword(s):  
Logic Circuit ◽  
Truth Table ◽  
The Other ◽  
Combinational Logic ◽  
Oscilloscope Screen ◽  
Sinusoidal Signals ◽  
Combinational Logic Circuit ◽  
Truth Tables

Abstract The objective of this paper is to design and implement a logic circuit prober to display truth tables of a three input combinational logic circuit. The truth table is to be as “1” and “0” on an ordinary 60 MHz oscilloscope. This paper meets this objective by using Lissajous Patterns to plot a “0” or a “1” on the oscilloscope screen. To plot a “0” on the oscilloscope screen, two sinusoidal signals in quadrature are supplied to the two inputs of the oscilloscope with the scope set to X-Y mode. To plot a “1” on the oscilloscope, only the signal to the Y input is allowed to reach the oscilloscope screen. To display all the 32 patterns required to obtain a three input truth table, two staircase waveforms are employed. The staircase waveforms, one eight-step and the other four-step, are added to the two sinusoidal signals to shift the patterns along the X and Y directions to produce all the 32 patterns.

Symptom or Cause? A Case Study

2015 ◽  
Author(s):  
Anuradha Swaminathan ◽  
Joy Liao ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Analysis Data ◽  
Continuous Wave Laser ◽  
Electrical Failure ◽  
Root Cause ◽  
First Case ◽  
Successful Analysis ◽  
28 Nm

Abstract Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.

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