Spectroscopic and capacitance–voltage characterization of thin aminopropylmethoxysilane films doped with copper phthalocyanine, tris(dimethylvinylsilyloxy)–POSS and fullerene cages

2012 ◽  
Vol 258 (10) ◽  
pp. 4213-4221 ◽  
Author(s):  
Jolanta Klocek ◽  
Karsten Henkel ◽  
Krzysztof Kolanek ◽  
Ehrenfried Zschech ◽  
Dieter Schmeißer
Keyword(s):  
Copper Phthalocyanine ◽  
Capacitance Voltage

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

The Ferroelectric and Electrical Properties of CaBi4Ti4O15 Thin Films Prepared by Sol-Gel Technology

2011 ◽  
Vol 239-242 ◽  
pp. 891-894 ◽  
Author(s):  
Tsung Fu Chien ◽  
Jen Hwan Tsai ◽  
Kai Huang Chen ◽  
Chien Min Cheng ◽  
Chia Lin Wu
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Sol Gel ◽  
Morphological Characterization ◽  
Experimental Result ◽  
X Ray Diffraction ◽  
Solution Deposition ◽  
Capacitance Voltage ◽  
Preferential Crystal Orientation

In this study, thin films of CaBi4Ti4O15with preferential crystal orientation were prepared by the chemical solution deposition (CSD) technique on a SiO2/Si substrate. The films consisted of a crystalline phase of bismuth-layer-structured dielectric. The as-deposited CaBi4Ti4O15thin films were crystallized in a conventional furnace annealing (RTA) under the temperature of 700 to 800°C for 1min. Structural and morphological characterization of the CBT thin films were investigated by X-ray diffraction (XRD) and field-emission scanning electron microscope (FE-SEM). The impedance analyzer HP4294A and HP4156C semiconductor parameters analyzer were used to measurement capacitance voltage (C-V) characteristics and leakage current density of electric field (J-E) characteristics by metal-ferroelectric-insulator- semiconductor (MFIS) structure. By the experimental result the CBT thin film in electrical field 20V, annealing temperature in 750°C the CBT thin film leaks the electric current is 1.88x10-7A/cm2and the memory window is 1.2V. In addition, we found the strongest (119) peak of as-deposited thin films as the annealed temperature of 750°C

Capacitance-Voltage Characterization of LPCVD-Silicon Oxynitride Films

2001 ◽  
Vol 187 (2) ◽  
pp. 493-498 ◽  
Author(s):  
A. Szekeres ◽  
S. Alexandrova ◽  
M. Modreanu
Keyword(s):  
Silicon Oxynitride ◽  
Capacitance Voltage

Capacitance-voltage and deep-level-transient spectroscopy characterization of defects near SiO2/SiC interfaces

2011 ◽  
Vol 109 (6) ◽  
pp. 064514 ◽  
Author(s):  
A. F. Basile ◽  
J. Rozen ◽  
J. R. Williams ◽  
L. C. Feldman ◽  
P. M. Mooney
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

Characterization of Nanocrystalline p-CuO/n-Si Hetrojunction Prepared by RF-Sputtering

2014 ◽  
Vol 1024 ◽  
pp. 120-123
Author(s):  
Nezar Gassem Elfadill ◽  
M. Roslan Hashim ◽  
Khaled M. Chahrour ◽  
Chun Sheng Wang
Keyword(s):  
Cupric Oxide ◽  
Pure Copper ◽  
Rf Sputtering ◽  
Saturation Current ◽  
Font Size ◽  
X Ray Diffraction ◽  
Single Crystalline ◽  
Current Voltage ◽  
Capacitance Voltage

Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif";}Nanocrystalline cupric oxide (CuO) film was prepared by sputtering of pure copper metal on n-type single crystalline Si substrate under argon-oxygen ambient. Structural and morphological analyses of the as-deposited CuO films were performed by X-ray diffraction (XRD) diffractometer and Field Emission Scanning Electron Microscopy (FESEM). The results show Single crystalline granular nanocrystalline (002) CuO films, with 18 nm crystallite size. Current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed for p-CuO/n-Si hetrojunction. Diode parameters such as saturation current (Is=9.5E-6 A) and ideality factor (n=1.86) were extracted from the dark I-V characteristics. Potential barrier height of the junction (ϕi=1.1V) was revealed from (1/C2- V) plot. Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif";}

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