A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.
Modern mineral processing plants utilise fault detection and diagnosis to minimise time spent under faulty conditions. However, a fault originating in one plant section (PS) can propagate throughout the entire plant, obscuring its root cause. Causality analysis identifies the cause–effect relationships between process variables and presents them in a causality map to inform root cause identification. This paper presents a novel hierarchical approach for plant-wide causality analysis that decreases the number of nodes in a causality map, improving interpretability and enabling causality analysis as a tool for plant-wide fault diagnosis. Two causality maps are constructed in subsequent stages: first, a dimensionally reduced, plant-wide causality map used to localise the fault to a PS; second, a causality map of the identified PS used to identify the root cause. The hierarchical approach accurately identified the true root cause in a well-understood case study; its plant-wide map consisted of only three nodes compared to 15 nodes in the standard causality map and its transitive reduction. The plant-wide map required less fault-state data, time series in the order of hours or days instead of weeks or months, further motivating its application in rapid root cause analysis.
Abstract
One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]
Abstract
This report summarizes the analysis of 0.18µm Flash ROM technology qualification failure cases at Macronix. The cases include single cell read failures, erase/program function failures, and high temperature storage test failures. Electrical analysis, EMMI and physical check by chemical de-processing, parallel lapping, FIB, SEM, PVC and TEM techniques were employed to identify the failure mechanisms, root causes, and solutions. From this study, improvements were achieved in process defect density, test fault coverage and product reliability of the 0.18µm Flash ROM technology.
Abstract
This paper describes the detailed process of failure analysis (FA) of a 16-bit transceiver. The FA included six steps: electronic parametric testing, visual inspection, optical beam induced resistance change to isolate failure location, SEM inspection of the breakdown, electro static discharge (ESD) root identification, and ESD test to prove the identification. FA showed that the short circuit was the result of a breakdown between the I/O resistor and the substrate, and the cause of the breakdown was most likely an ESD event. In a series of electrical over stress/ESD tests performed, the field failure signature was replicated with a MM ESD model, thereby identifying the root cause of the ESD failure.
Abstract
Product dimensional quality is one of the most important topics in machining processes. However, limited research has been done on the dimensional control and root cause identification methodologies in multi-station machining processes. This paper will study the stream of variation (SOV) problem by developing a new type of model — State Space Model — to describe the dimensional deviation of the multistation machining processes. A process level diagnostic methodology is also developed. A case study is presented to illustrate the developed modeling and diagnostics methodology.
Abstract
A case study is presented of a core CPU product where FA/FI debug is performed for an ESD-related pin leakage issue on an IO family to root cause and qualify the product. A Powered TIVA technique is used to localize the damage to the termination resistor circuitry of the affected IO block when the pin is tristated using a device tester. Failure characterization shows a gate to drain short on the transistor, with nanoprobing confirming a solid short on gate to drain and TEM finding a short at the location indicated by the TIVA hits.
Abstract
Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.
Abstract
The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.
Abstract
An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.
Root Cause Analysis of a Printed Circuit Board (PCB) Failure in a Public Transport Communication System