Accurate analytical drain current model for a nanoscale fully-depleted SOI MOSFET

2015 ◽  
Vol 103 ◽  
pp. 154-161 ◽  
Author(s):  
Mohammad K. Anvarifard ◽  
Ali A. Orouji
2018 ◽  
Vol 55 ◽  
pp. 75-81 ◽  
Author(s):  
C. Usha ◽  
Palanichamy Vimala

In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.


2019 ◽  
Vol 34 (02) ◽  
pp. 2050023
Author(s):  
Zhen Zhu ◽  
Junhao Chu

For fully-depleted polycrystalline silicon thin film transistors including both tail and deep acceptor-like trap states in the bulk and interface charges, a channel-potential-based surface potential model (including front and back surface potential) and a turn-on DC channel-potential-based drain current model are proposed with the effect of the back surface potential considered. Firstly, a channel-potential-based surface potential model is obtained by introducing a channel-potential-based front and back surface potential equation and a channel-potential-based equation describing the coupling effect of the front and back surface potential. Contributions of active acceptors, electrons and trapped charges are all taken into account in this coupling effect. Moreover, by integrating the electron concentration, vertically to the front poly-Si/oxide interface, in the inversion layer, using the average electric field concept and considering the effect of channel potential in the potential of the inversion layer’s ending point, the areal density of the inversion charge is deduced. Furthermore, a channel-potential-based drain current model, avoiding the double numerical integration, is developed with the merit of relative simplification in calculation. By using recursive Simpson rules, this drain current model is calculated by numerical integration with the examining condition. And the above proposed models are verified by 2D-device simulation from MEDICI.


Silicon ◽  
2020 ◽  
Author(s):  
Vimal Kumar Mishra ◽  
Sunil Pandey ◽  
Nilesh Anand Srivastava ◽  
R. K. Chauhan

2011 ◽  
Vol 110-116 ◽  
pp. 3332-3337
Author(s):  
Shan Shan Qin ◽  
He Ming Zhang ◽  
Hui Yong Hu ◽  
Xiao Bo Xu ◽  
Xiao Yan Wang

A subthreshold current model for fully depleted strained Si on insulator (FD SSOI) MOSFET is developed by solving the two-dimensional (2D) Poisson equation and the conventional drift-diffusion theory. Model verification is carried out using device simulator ISE. Good agreement is obtained between the model’s calculations and the simulated results. This subthreshold current model provides valuable reference to the FD-SSOI MOSFET design.


2000 ◽  
Vol 21 (5) ◽  
pp. 239-241 ◽  
Author(s):  
J.B. Roldan ◽  
F. Gamiz ◽  
J.A. Lopez-Villanueva ◽  
P. Cartujo-Cassinello

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.


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