scholarly journals Design and Reliability Assessment of Novel 3D-IC Packaging

2016 ◽  
Vol 33 (2) ◽  
pp. 193-203 ◽  
Author(s):  
Y.-F. Su ◽  
K.-N. Chiang ◽  
Steven Y. Liang
Keyword(s):  
Electronic Packaging ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Material Design ◽  
Circuit Board ◽  
Wafer Level ◽  
Element Analysis ◽  
Moore’S Law ◽  
Moore's Law

AbstractPresently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Lei Shi ◽  
Lin Chen ◽  
David Wei Zhang ◽  
Evan Liu ◽  
Qiang Liu ◽  
...  
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Equivalent Stress ◽  
Circuit Board ◽  
Electrical Performance ◽  
Design Parameters ◽  
Wafer Level ◽  
Element Analysis

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Damage Path Simulation of Solder Joints in QFP

2005 ◽  
Author(s):  
Minoru Mukai ◽  
Kenji Hirohata ◽  
Hiroyuki Takahashi ◽  
Takashi Kawakami ◽  
Kuniaki Takahashi
Keyword(s):  
Crack Propagation ◽  
Present Method ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Fatigue Cracks ◽  
New Method ◽  
Circuit Board ◽  
Crack Model ◽  
Element Analysis ◽  
Electronic Package

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.

Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Jia Xi ◽  
Xinduo Zhai ◽  
Jun Wang ◽  
Donglun Yang ◽  
Mao Ru ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
High Stress ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Element Analysis ◽  
Drop Tests ◽  
Feni Alloy

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000224-000232 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Thermal Fatigue Analysis of PBGA Solder Joints With the Consideration of Damage Evolution

2000 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Keith Newman ◽  
Livia Hu
Keyword(s):  
Thermal Fatigue ◽  
Life Prediction ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Hysteresis Loops ◽  
Fatigue Analysis ◽  
Circuit Board ◽  
Element Analysis ◽  
Pcb Assembly ◽  
Plastic Ball

Abstract This paper presents a computational thermal fatigue analysis for the life prediction of solder joints in a plastic ball grid array-printed circuit board (PBGA-PCB) assembly. The PBGA has a full grid array of 256 solder balls with 1.0 mm ball pitch. The PCB is a 4-layer FR-4 laminate with a thickness of 1.57 mm (62 mils). The assembly is subjected to −40∼125°C thermal cycling (one-hour cycle). Finite element analysis is performed to obtain the creep hysteresis loops. Based on a previously developed model, the evolution of damage is considered in the life prediction of solder joints. Besides, PCBs with various thicknesses (40 mils and 20 mils) are investigated. The results from different cases are compared and discussed.

scholarly journals The Effect of Epoxy Polymer Addition in Sn-Ag-Cu and Sn-Bi Solder Joints

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin
Keyword(s):  
Solder Joint ◽  
Strain Energy ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Solder Paste ◽  
Element Analysis ◽  
Printed Circuit ◽  
Shock Testing ◽  
Polymer Addition

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.

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