Damage Path Simulation of Solder Joints in QFP

2005 ◽  
Author(s):  
Minoru Mukai ◽  
Kenji Hirohata ◽  
Hiroyuki Takahashi ◽  
Takashi Kawakami ◽  
Kuniaki Takahashi
Keyword(s):  
Crack Propagation ◽  
Present Method ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Fatigue Cracks ◽  
New Method ◽  
Circuit Board ◽  
Crack Model ◽  
Element Analysis ◽  
Electronic Package

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.

Thermal Fatigue Analysis of PBGA Solder Joints With the Consideration of Damage Evolution

2000 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Keith Newman ◽  
Livia Hu
Keyword(s):  
Thermal Fatigue ◽  
Life Prediction ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Hysteresis Loops ◽  
Fatigue Analysis ◽  
Circuit Board ◽  
Element Analysis ◽  
Pcb Assembly ◽  
Plastic Ball

Abstract This paper presents a computational thermal fatigue analysis for the life prediction of solder joints in a plastic ball grid array-printed circuit board (PBGA-PCB) assembly. The PBGA has a full grid array of 256 solder balls with 1.0 mm ball pitch. The PCB is a 4-layer FR-4 laminate with a thickness of 1.57 mm (62 mils). The assembly is subjected to −40∼125°C thermal cycling (one-hour cycle). Finite element analysis is performed to obtain the creep hysteresis loops. Based on a previously developed model, the evolution of damage is considered in the life prediction of solder joints. Besides, PCBs with various thicknesses (40 mils and 20 mils) are investigated. The results from different cases are compared and discussed.

scholarly journals The Effect of Epoxy Polymer Addition in Sn-Ag-Cu and Sn-Bi Solder Joints

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin
Keyword(s):  
Solder Joint ◽  
Strain Energy ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Solder Paste ◽  
Element Analysis ◽  
Printed Circuit ◽  
Shock Testing ◽  
Polymer Addition

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.

Large-Scale Damage Path Simulation for Solder Joints in a BGA Package

2013 ◽  
Author(s):  
Takahiro Omori ◽  
Kenji Hirohata ◽  
Tomoko Monda ◽  
Minoru Mukai
Keyword(s):  
Crack Propagation ◽  
Life Prediction ◽  
Large Scale ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Electronic Packages ◽  
Printed Circuit ◽  
Bga Package ◽  
The Relationship

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Lei Shi ◽  
Lin Chen ◽  
David Wei Zhang ◽  
Evan Liu ◽  
Qiang Liu ◽  
...  
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Equivalent Stress ◽  
Circuit Board ◽  
Electrical Performance ◽  
Design Parameters ◽  
Wafer Level ◽  
Element Analysis

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

scholarly journals Design and Reliability Assessment of Novel 3D-IC Packaging

2016 ◽  
Vol 33 (2) ◽  
pp. 193-203 ◽  
Author(s):  
Y.-F. Su ◽  
K.-N. Chiang ◽  
Steven Y. Liang
Keyword(s):  
Electronic Packaging ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Material Design ◽  
Circuit Board ◽  
Wafer Level ◽  
Element Analysis ◽  
Moore’S Law ◽  
Moore's Law

AbstractPresently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

Dynamic – Thermal Analyses of a Structurally Reconfigured Electronics Package Onboard Mini Satellite

2014 ◽  
Vol 592-594 ◽  
pp. 2117-2121 ◽  
Author(s):  
P. Veeramuthuvel ◽  
S. Jayaraman ◽  
Shankar Krishnapillai ◽  
M. Annadurai ◽  
A.K. Sharma
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Thermal Environment ◽  
Thermal Analyses ◽  
Simulation Models ◽  
Element Model ◽  
Circuit Board ◽  
Element Analysis ◽  
Transfer Path ◽  
Vibration Responses

The electronics package in a spacecraft is subjected to a variety of dynamic loads during launch phase and suitable thermal environment for the mission life. The dynamic and thermal analyses performed for a structurally reconfigured electronics package. Two different simulation models are developed to carry out the analyses. This paper discusses in two parts, in part-1, the vibration responses are determined at various critical locations, including on the Printed Circuit Board (PCB) for the vibration loads specified by launch vehicle using Finite Element Analysis (FEA). The mechanical properties of PCB are determined from the test specimens, which are then incorporated in the finite element model. In part-2, the steady-state temperature distributions on the components and on the PCB are determined, to check the effectiveness of heat transfer path from the components to the base of the package and to verify the predicted values are within the acceptable temperature limits specified. The predicted temperature values are then compared with on-orbit observations.

Validation of the Critical Strain-Based Methodology for Evaluating the Mechanical Safety of Ball Grid Array Solder Joints in a Launch Random Vibration Environment

2021 ◽  
Author(s):  
Tae-Yong Park ◽  
Hyun-Ung Oh
Keyword(s):  
Fatigue Life ◽  
Random Vibration ◽  
Critical Strain ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mechanical Design ◽  
Ball Grid Array ◽  
Primary Objective ◽  
Circuit Board ◽  
Analytical Approaches

Abstract To overcome the theoretical limitations of Steinberg's theory for evaluating the mechanical safety of the solder joints of spaceborne electronics in a launch random vibration environment, a critical strain-based methodology was proposed and validated in a previous study. However, for the critical strain-based methodology to be used reliably in the mechanical design of spaceborne electronics, its effectiveness must be validated under various conditions of the package mounting locations and the first eigenfrequencies of a printed circuit board (PCB); achieving this validation is the primary objective of this study. For the experimental validation, PCB specimens with ball grid array packages mounted on various board locations were fabricated and exposed to a random vibration environment to assess the fatigue life of the solder joint. The effectiveness of the critical strain-based methodology was validated through a comparison of the fatigue life of the tested packages and their margin of safety, which was estimated using various analytical approaches.

In-Plane Electromagnetic Generator Fabricated on Printed Circuit Board Technology

2013 ◽  
Vol 479-480 ◽  
pp. 524-529
Author(s):  
C.T. Pan ◽  
F.T. Hsu ◽  
C.C. Nien ◽  
Z.H. Liu ◽  
Y.J. Chen ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Energy Harvester ◽  
Cost Effective ◽  
Circuit Board ◽  
Outer Diameter ◽  
Magnetic Element ◽  
Induced Voltage ◽  
Element Analysis ◽  
Printed Circuit ◽  
Electromagnetic Generator

Small and efficient energy harvesters, as a renewable power supply, draw lots of attention in the last few years. This paper presents a planar rotary electromagnetic generator with copper coils fabricated by using printed circuit board (PCB) as inductance and Nd-Fe-B magnets as magnetic element. Coils are fabricated on PCB, which is presumably cost-effective and promising methods. 28-pole Nd-Fe-B magnets with outer diameter of 50 mm and thickness of 2 mm was sintered and magnetized, which can provide magnetic field of 1.44 Tesla. This harvester consists of planar multilayer with multi-pole coils and multi-pole permanent magnet, and the volume of this harvester is about 50x50x2.5 mm3. Finite element analysis is used to design energy harvesting system, and simulation model of the energy harvester is established. In order to verify the simulation, experiment data are compared with simulation result. The PCB energy harvester prototype can generate induced voltage 0.61 V and 13.29mW output power at rotary speed of 4,000 rpm.

Kinetics of Cavity Growth In Solder Joints During Thermal Cycle

1984 ◽  
Vol 40 ◽  
Author(s):  
Donald S. Stone ◽  
Thomas R. Homa ◽  
Che-Yu Li
Keyword(s):  
Printed Circuit Board ◽  
Solder Joints ◽  
Cavity Growth ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
State Variable ◽  
Circuit Board Assembly ◽  
Variable Equation ◽  
Chip Carrier ◽  
Kinetics Of

AbstractGrain boundary cavity growth in solder joints during thermal fatigue is analyzed. The stress cycle profile is estimated based on a geometrically simplified model of a ceramic chip carrier - printed circuit board assembly and a state variable equation for plastic flow in the solder.

Sign in / Sign up

Export Citation Format

Share Document