Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

2018 ◽  
Vol 140 (1) ◽  
Author(s):  
Lei Shi ◽  
Lin Chen ◽  
David Wei Zhang ◽  
Evan Liu ◽  
Qiang Liu ◽  
...  
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Equivalent Stress ◽  
Circuit Board ◽  
Electrical Performance ◽  
Design Parameters ◽  
Wafer Level ◽  
Element Analysis

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

scholarly journals Design and Reliability Assessment of Novel 3D-IC Packaging

2016 ◽  
Vol 33 (2) ◽  
pp. 193-203 ◽  
Author(s):  
Y.-F. Su ◽  
K.-N. Chiang ◽  
Steven Y. Liang
Keyword(s):  
Electronic Packaging ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Coefficient Of Thermal Expansion ◽  
Material Design ◽  
Circuit Board ◽  
Wafer Level ◽  
Element Analysis ◽  
Moore’S Law ◽  
Moore's Law

AbstractPresently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Dynamic – Thermal Analyses of a Structurally Reconfigured Electronics Package Onboard Mini Satellite

2014 ◽  
Vol 592-594 ◽  
pp. 2117-2121 ◽  
Author(s):  
P. Veeramuthuvel ◽  
S. Jayaraman ◽  
Shankar Krishnapillai ◽  
M. Annadurai ◽  
A.K. Sharma
Keyword(s):  
Finite Element ◽  
Printed Circuit Board ◽  
Thermal Environment ◽  
Thermal Analyses ◽  
Simulation Models ◽  
Element Model ◽  
Circuit Board ◽  
Element Analysis ◽  
Transfer Path ◽  
Vibration Responses

The electronics package in a spacecraft is subjected to a variety of dynamic loads during launch phase and suitable thermal environment for the mission life. The dynamic and thermal analyses performed for a structurally reconfigured electronics package. Two different simulation models are developed to carry out the analyses. This paper discusses in two parts, in part-1, the vibration responses are determined at various critical locations, including on the Printed Circuit Board (PCB) for the vibration loads specified by launch vehicle using Finite Element Analysis (FEA). The mechanical properties of PCB are determined from the test specimens, which are then incorporated in the finite element model. In part-2, the steady-state temperature distributions on the components and on the PCB are determined, to check the effectiveness of heat transfer path from the components to the base of the package and to verify the predicted values are within the acceptable temperature limits specified. The predicted temperature values are then compared with on-orbit observations.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties

2021 ◽  
Vol 21 (5) ◽  
pp. 2987-2991
Author(s):  
Geumtaek Kim ◽  
Daeil Kwon
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Material Properties ◽  
Coefficient Of Thermal Expansion ◽  
Input Output ◽  
Wafer Level ◽  
High Input ◽  
Element Analysis ◽  
Packaging Process ◽  
Wafer Level Packaging

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Damage Path Simulation of Solder Joints in QFP

2005 ◽  
Author(s):  
Minoru Mukai ◽  
Kenji Hirohata ◽  
Hiroyuki Takahashi ◽  
Takashi Kawakami ◽  
Kuniaki Takahashi
Keyword(s):  
Crack Propagation ◽  
Present Method ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Fatigue Cracks ◽  
New Method ◽  
Circuit Board ◽  
Crack Model ◽  
Element Analysis ◽  
Electronic Package

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Dynamic Analysis of HSDB System and Evaluation of Boundary Non-linearity through Experiments

2016 ◽  
Vol 66 (3) ◽  
pp. 210
Author(s):  
K. Chandrakar ◽  
P.L. Venkateshwara Rao ◽  
P. Rajendran ◽  
C. Satyanarayana
Keyword(s):  
Finite Element ◽  
Natural Frequency ◽  
High Speed ◽  
Printed Circuit Board ◽  
Structural Integrity ◽  
Mechanical Design ◽  
Circuit Board ◽  
Element Analysis ◽  
Maximum Acceleration ◽  
Vibration Tests

<p class="FAIMTextBody">This paper deals with mechanical design and development of high speed digital board (HSDB) system which consists of printed circuit board (PCB) with all electronic components packaged inside the cavity for military application. The military environment poses a variety of extreme dynamic loading conditions, namely, quasi static, vibration, shock and acoustic loads that can seriously degrade or even cause failure of electronics. The vibrational requirement for the HSDB system is that the natural frequency should be more than 200 Hz and sustain power spectrum density of 14.8 Grms in the overall spectrum. Structural integrity of HSDB is studied in detail using finite element analysis (FEA) tool against the dynamic loads and configured the system. Experimental vibration tests are conducted on HSDB with the help of vibration shaker and validated the FE results. The natural frequency and maximum acceleration response computed from vibration tests for the configured design were found. The finite element results show a good correlation with the experiment results for the same boundary conditions. In case of fitment scenario of HSDB system, it is observed that the influence of boundary non-linearity during experiments. This influence of boundary non-linearity is evaluated to obtain the closeout of random vibration simulation results.</p>

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