A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications

2020 ◽  
Vol 12 (6) ◽  
pp. 825-830
Author(s):  
Abhijit Kumar Mukhopadhyay
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Large Scale ◽  
Average Power ◽  
Higher Order ◽  
Average Power Consumption ◽  
Xnor Gate ◽  
Large Scale Integration ◽  
Mathematical Equations ◽  
Scale Integration

This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.

Directed Assembly of Metal Oxide Nanobelts With Microsystems Into Integrated Nanosensors

2004 ◽  
Author(s):  
Choongho Yu ◽  
Qing Hao ◽  
Li Shi ◽  
Dae-Jin Kang ◽  
Xiangyang Kong ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Gas Sensors ◽  
Large Scale ◽  
Tin Dioxide ◽  
Electrical Conductance ◽  
Directed Assembly ◽  
Large Scale Integration ◽  
Sno2 Nanobelts ◽  
Scale Integration

Single-crystalline tin dioxide (SnO2) nanobelts have been assembled with microfabricated suspended heaters as low-power, sensitive gas sensors. With less than 4 mW power consumption of the micro-heater, the nanobelt can be heated up to 500°C. The electrical conductance of the heated nanobelt was found to be highly stable and sensitive to toxic and inflammable gas species including dimethyl methyl phosphonate (DMMP), nitrogen dioxide (NO2), and ethanol. The experiment is a step towards the large scale integration of nanomaterials with microsystems, and such integration via a directed assembly approach can potentially enable the fabrication of low-power, sensitive, and selective integrated nanosensor systems.

scholarly journals An efficient high speed, high frequency domino-logic based circuit

2018 ◽  
Vol 7 (2) ◽  
pp. 252
Author(s):  
Mahdi Zare ◽  
Hossein Manouchehrpour ◽  
Ahmad Esmaeilkhah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Considerable Improvement ◽  
Low Power Consumption ◽  
Domino Logic ◽  
Large Scale Integration ◽  
Scale Integration

As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit’s speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.  

scholarly journals Reversible logic in pipelined low power vedic multiplier

2019 ◽  
Vol 16 (3) ◽  
pp. 1265
Author(s):  
Ansiya Eshack ◽  
S. Krishnakumar
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Large Scale ◽  
Optical Computing ◽  
Digital Signal ◽  
Logic Gates ◽  
Reversible Logic ◽  
Large Scale Integration ◽  
Time Required ◽  
Scale Integration

<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

scholarly journals Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

2018 ◽  
Vol 51 (7-8) ◽  
pp. 235-242 ◽  
Author(s):  
Arulmurugan Azhaganantham ◽  
Murugesan Govindasamy
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Power Distribution ◽  
Large Scale ◽  
Heat Dissipation ◽  
Peak Temperature ◽  
Heating Event ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

scholarly journals A configurable fluorescence sensing front-end for ultra-low power and high sensitivity applications

2021 ◽  
Author(s):  
Maryam Rafati ◽  
Seyed Ruhallah Qasemi ◽  
Atila Alvandpour
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Excitation Frequency ◽  
Average Power ◽  
High Sensitivity ◽  
Current Noise ◽  
Fluorescence Sensing ◽  
Ultra Low Power ◽  
Front End ◽  
Average Power Consumption

AbstractThis paper presents an ultra-low power, high sensitivity configurable CMOS fluorescence sensing front-end for implantable biosensors at single-cell level measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, an ambient light canceling technique is proposed to make the sensor operate under different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is designed and fabricated in a 0.35 µm standard CMOS technology, and the measurement results are presented. The minimum integrated input-referred current noise is measured as 1.07 pA with the total average power consumption of 61.8 µW at an excitation frequency of 80 Hz. For ultra-low-power configuration, the front-end has an average power consumption of 119 nW and input integrated current noise of 210 pA at an excitation frequency of 20 kHz.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

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