Design of Phase Frequency Detector (PFD),Charge Pump (CP) and Programmable Frequency Divider for PLL in 0.18um CMOS Technology

2018 ◽  
Author(s):  
Anim Arifah Ahmad ◽  
Sawal Hamid Md Ali ◽  
Noorfazila Kamal ◽  
Siti Raudzah Abdul Rahman ◽  
Masuri Othman
Keyword(s):  
Charge Pump ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Programmable Frequency Divider

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

scholarly journals A Low-voltage Programmable Frequency Divider with Wide Input Frequency Range

2018 ◽  
Vol 17 ◽  
pp. 01007
Author(s):  
Yilong Liao ◽  
Xiangning Fan
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Input Frequency ◽  
Maximum Frequency ◽  
Frequency Division ◽  
Frequency Range ◽  
Division Ratio ◽  
Custom Design ◽  
Programmable Frequency Divider

A low-voltage programmable frequency divider with wide input frequency range is fabricated in standard 0.18µm TSMC RF CMOS technology and presented in this paper. Considering the frequency division ratio of dual-modulus prescaler is relatively smaller, a programmable divider with full custom design is used to increase the frequency division ratio and the maximum operating frequency. The frequency division ratio of the programmable frequency divider covers from 64 to 255. And the measured results show that the programmable divider works correctly when the input frequency varies from 0.5 GHz to 6.0 GHz, with 1V supply. Besides, the power consumption is 3.5 mA at the maximum frequency of 6.0 GHz.

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

scholarly journals Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

2021 ◽  
Vol 23 (11) ◽  
pp. 184-197
Author(s):  
Pawan Srivastava ◽  
◽  
Dr. Ram Chandra Singh Chauhan ◽  
Keyword(s):  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Process Variations ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Voltage Controlled Oscillator ◽  
Phase Frequency Detector ◽  
Power Efficient ◽  
Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

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