scholarly journals Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor

2020 ◽  
Vol 77 ◽  
pp. 04003
Author(s):  
Mark Ogbodo ◽  
Khanh Dang ◽  
Fukuchi Tomohide ◽  
Abderazek Abdallah
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Fault Tolerant ◽  
Three Dimensional ◽  
Spiking Neuron ◽  
Chip Area ◽  
Processor Core ◽  
Neuromorphic Systems ◽  
Event Driven ◽  
On Chip

Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

scholarly journals Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 90436-90452 ◽  
Author(s):  
The H. Vu ◽  
Ogbodo Mark Ikechukwu ◽  
Abderazek Ben Abdallah
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Three Dimensional ◽  
Neuromorphic Systems

scholarly journals Design of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique

2020 ◽  
pp. 62-65
Author(s):  
Pyasa Dileep and A Satyanarayana B Sangeeth Kumar,
Keyword(s):  
Low Power ◽  
High Speed ◽  
Portable Devices ◽  
Design Constraints ◽  
Innovative Design ◽  
Chip Area ◽  
Recent Trends ◽  
On Chip ◽  
Minimal Hardware ◽  
Selection Of

In this paper we are design a circuit based on data selector and distributor networks in which we will not realize the circuit based upon the expressions but off course the circuit which have designed will have internally some expression. In the recent trends the need for low power and less on-chip area is on high note for the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative design of 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDI Cell as well as selection of primary inputs to the terminals of GDI cell. 8-Bit GDI based Comparator will be designed and simulated using Tanner EDATool. Comparator has three main outputs where it can compare the weight of two words and generates three functions. GDI has the advantage of low power consumption because the total number of logic devices needed willbe less and it can also operate with high speed due to affective realization of logic using minimal hardware. Comparator circuits is designed using tanner tools and also observe the simulation results in H-SPICE attaining low power and less delay.

scholarly journals DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 122
Author(s):  
Jiemin Li ◽  
Shancong Zhang ◽  
Chong Bao
Keyword(s):  
Error Detection ◽  
Integrated Circuit ◽  
Large Scale ◽  
Fault Tolerant ◽  
Soft Errors ◽  
Implementation Process ◽  
Radiation Environment ◽  
Cmos Integrated Circuit ◽  
Processor Core ◽  
The Impact

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

scholarly journals Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System

2021 ◽  
Vol 15 ◽  
Author(s):  
Abderazek Ben Abdallah ◽  
Khanh N. Dang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Large Scale ◽  
Three Dimensional ◽  
Network On Chip ◽  
Spike Timing ◽  
Dimensional Structure ◽  
Spiking Neural Network ◽  
3D Ics ◽  
On Chip

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

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