The large-scale integration of high-performance silicon nanowire field effect transistors

2009 ◽  
Vol 20 (41) ◽  
pp. 415202 ◽  
Author(s):  
Qiliang Li ◽  
Xiaoxiao Zhu ◽  
Yang Yang ◽  
Dimitris E Ioannou ◽  
Hao D Xiong ◽  
...  
2018 ◽  
Vol 143 ◽  
pp. 97-102 ◽  
Author(s):  
M. Legallais ◽  
T.T.T. Nguyen ◽  
M. Mouis ◽  
B. Salem ◽  
E. Robin ◽  
...  

1982 ◽  
Vol 53 (8) ◽  
pp. 5951-5958 ◽  
Author(s):  
R. E. Thorne ◽  
S. L. Su ◽  
W. Kopp ◽  
R. Fischer ◽  
T. J. Drummond ◽  
...  

2021 ◽  
Author(s):  
Yejin Yang ◽  
Juhee Jeon ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.


2012 ◽  
Vol 23 (39) ◽  
pp. 395202 ◽  
Author(s):  
O Shirak ◽  
O Shtempluck ◽  
V Kotchtakov ◽  
G Bahir ◽  
Y E Yaish

2012 ◽  
Vol 584 ◽  
pp. 428-432 ◽  
Author(s):  
Mayank Chakraverty ◽  
Harish M. Kittur

High gate leakage current, as a central problem, has decelerated the downscaling of minimum feature size of the field effect transistors In this paper, a combination of density functional theory and non equilibrium Green’s function formalism has been applied to the atomic scale calculation of the tunnel currents through CeO2, Y2O3, TiO2 and Al2O3 dielectrics in MOSFETs. The tunnel currents for different bias voltages applied to Si/Insulator/Si systems have been obtained along with tunnel conductance v/s bias voltage plots for each system. The results are in agreement to the use of high dielectric constant materials as gate dielectric so as to enable further downscaling of MOSFETs with reduced gate leakage currents thereby enabling ultra large scale integration. When used as dielectric, TiO2 exhibits extremely low tunnel currents followed by Y2O3 while CeO2 and Al2O3 exhibit high tunnel currents through them at certain bias voltages.


Nano Research ◽  
2011 ◽  
Vol 4 (10) ◽  
pp. 1005-1012 ◽  
Author(s):  
Ruo-Gu Huang ◽  
Douglas Tham ◽  
Dunwei Wang ◽  
James R. Heath

2020 ◽  
Author(s):  
Sunbin Hwang ◽  
Minji Kang ◽  
Aram Lee ◽  
Sukang Bae ◽  
Seoung-Ki Lee ◽  
...  

Abstract Electronic textiles have been considered one of the desired device platforms due to their dimensional compatibility with fabrics by weaving them with yarn. However, the existing electronic textile platforms are generally composed of only one type of electronic component with a single function on a fiber substrate because of processing challenges. A precise connecting process between each electronic fiber is essential to configure the desired electronic circuits or systems. Here we present a chip on a fiber, a new electronic fiber platform, by introducing large scale integration of electronic device or circuit components onto a one-dimensional microfiber substrate. The electronic components such as transistors, inverters, ring oscillators, and thermocouples were integrated together onto the outer surface of a fiber substrate with precise semiconductor and electrode patterns. Our results show that the electronic components can be integrated on a single fiber with reliable operation. We evaluate the electronic properties of the chip on a fiber as a multifunctional electronic textile platform by testing their switching and data processing, as well as sensing or transducing units for detecting optical/thermal signals. The demonstration of the chip on a fiber suggests significant proof of concepts for realization of high performance with wearable electronic textile systems.


Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.


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