Multi-chip front-end electronics LYRA for X and γ Ray detector for HERMES mission

2021 ◽  
Vol 16 (12) ◽  
pp. T12013
Author(s):  
M. Gandola ◽  
F. Mele ◽  
M. Grassi ◽  
P. Malcovati ◽  
G. Bertuccio

Abstract We present the experimental results of the Application Specific Integrated Circuit (ASIC), called LYRA, specifically designed for the High-Energy Rapid Modular Ensemble of Satellites (HERMES) mission concept, a constellation of nano-satellites able to detect and localize high-energy rapid transient events (up to 2.2 MeV) as the Gamma Ray Bursts (GRBs) from the deep space. LYRA has been desied for the detection system composed by a combination of Gadolinium Aluminum Gallium Garnet (GAGG) scintillators for high-energy photons, coupled to a matrix of 120 silicon drift detectors (SDD), used for detecting both scintillation light and low-energy photons. The LYRA ASIC has been conceived with a multi-chip architecture: 120 LYRA Front-End chips (LYRA-FE) are placed in close proximity to the anodes of the SDD matrix for a first processing of the detector signals and trasmit them in current mode to four 32-channel LYRA Back-End chips (LYRA-BE) to complete the elaboration. The requirements that the LYRA ASIC have to fulfill for the HERMES project are challenging: the maximum input energy measured in Silicon must reach 120 keV — corresponding to 2.2 MeV on GAGG — with a linearity error below 1%, the electronic noise must be less then 30 el. r.m.s. and the power consumption less then 1 mW per channel in a system with 120 channels working in parallel. The characterization of LYRA has been carried out on a dedicated test board, coupling one channel of the ASIC with a 25 mm2 SDD. An input full scale range of 5.2 fC and an electronic noise of 22 el. r.m.s. have been measured at -33∘C with a power consumption of 745 µW per channel.

2013 ◽  
Vol 25 (1) ◽  
pp. 169-172
Author(s):  
吴福源 Wu Fuyuan ◽  
张凤娜 Zhang Fengna ◽  
高永凤 Gao Yongfeng ◽  
陶仕达 Tao Shida ◽  
王云海 Wang Yunhai ◽  
...  

2020 ◽  
Vol 2 (2) ◽  
pp. 92-99
Author(s):  
Ms. Christina G.

Future Wi-Fi, 5G Cellular and millimetre-wave (mmWave) will depend on highly directional links in order to prevail over exuberant path loss experienced in the different bands of frequency. However, in order to establish these type of links, the receiver and transmitter need mutual discovery which will result in high energy consumption and large latency. The proposed work deals with reduction of energy consumption and latency significantly with the help of a fully digital front-end. The digital beamformer will receive the spatial samples within a shot, from all directions. However, in analog front-ends, sampling is allowed for beamforming in one particular direction at a time resulting in the time period in which the mobile is “on” for longer. This will result in an increase in energy consumption by more than four times for the analog front-end when compared with digital front-ends, taking into consideration the antenna arrays’ size. However, from the power consumption point of view, using a fully digital beamforming post beam discovery is not recommended. Hence in order to overcome this drawback, a digital beamformer coupled with a 4-bit A-D convertor with low resolution is proposed. The use of low resolution will decrease the power consumption such that it is in the same zone as that of analog beam forming while it is possible to make use of the fully digital beamforming spatial multiplexing capabilities resulting in improved energy efficiency and reduced discovery latency.


2015 ◽  
Vol 781 ◽  
pp. 168-171
Author(s):  
Ekkapong Saising ◽  
Thanate Pattanathadapong ◽  
Pipat Prommee

This paper presents the realization of CMOS-based current-mode Elliptic ladder band-pass filter by using doubly terminated Elliptic RLC ladder band-pass filter prototype [1], [2]. The proposed circuit contains lossless integrators, lossy integrators and multiple outputs current gains. The frequency response of the proposed circuit can be electronically tuned between 1 MHz and 100 MHz by adjusting bias current between 1μA and 1,000 μA. The proposed circuit uses 1.5 V power supply and 0.1 W power consumption. The passive elements that contained in the proposed filter are only grounded capacitors without using other passive elements that can make this filter suitable for integrated circuit. PSPICE simulation results are carried out by using TSMC 0.18 μm technology and agreed well with the theory.


Author(s):  
J. B. Warren

Electron diffraction intensity profiles have been used extensively in studies of polycrystalline and amorphous thin films. In previous work, diffraction intensity profiles were quantitized either by mechanically scanning the photographic emulsion with a densitometer or by using deflection coils to scan the diffraction pattern over a stationary detector. Such methods tend to be slow, and the intensities must still be converted from analog to digital form for quantitative analysis. The Instrumentation Division at Brookhaven has designed and constructed a electron diffractometer, based on a silicon photodiode array, that overcomes these disadvantages. The instrument is compact (Fig. 1), can be used with any unmodified electron microscope, and acquires the data in a form immediately accessible by microcomputer.Major components include a RETICON 1024 element photodiode array for the de tector, an Analog Devices MAS-1202 analog digital converter and a Digital Equipment LSI 11/2 microcomputer. The photodiode array cannot detect high energy electrons without damage so an f/1.4 lens is used to focus the phosphor screen image of the diffraction pattern on to the photodiode array.


Author(s):  
Gennady Sergeevich, Minasyants ◽  
◽  
Tamara Mihailovna, Minasyants ◽  
Vladimir Mihailovich, Tomozov ◽  
◽  
...  

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3635 ◽  
Author(s):  
Guoming Zhang ◽  
Xiaoyu Ji ◽  
Yanjie Li ◽  
Wenyuan Xu

As a critical component in the smart grid, the Distribution Terminal Unit (DTU) dynamically adjusts the running status of the entire smart grid based on the collected electrical parameters to ensure the safe and stable operation of the smart grid. However, as a real-time embedded device, DTU has not only resource constraints but also specific requirements on real-time performance, thus, the traditional anomaly detection method cannot be deployed. To detect the tamper of the program running on DTU, we proposed a power-based non-intrusive condition monitoring method that collects and analyzes the power consumption of DTU using power sensors and machine learning (ML) techniques, the feasibility of this approach is that the power consumption is closely related to the executing code in CPUs, that is when the execution code is tampered with, the power consumption changes accordingly. To validate this idea, we set up a testbed based on DTU and simulated four types of imperceptible attacks that change the code running in ARM and DSP processors, respectively. We generate representative features and select lightweight ML algorithms to detect these attacks. We finally implemented the detection system on the windows and ubuntu platform and validated its effectiveness. The results show that the detection accuracy is up to 99.98% in a non-intrusive and lightweight way.


Author(s):  
Raja Krishnamoorthy ◽  
E. Kavitha ◽  
V. Beslin Geo ◽  
K.S.R. Radhika ◽  
C. Bharatiraja

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