Dry etching of silicon carbide in ICP with high anisotropy and etching rate

AbstractHigh-quality, ultra-precise processing of surfaces is of high importance for high-tech industry and requires a good depth control of processing, a low roughness of the machined surface and as little as possible surface and subsurface damage but cannot be realized by laser ablation processes. Contrary, electron/ion beam, plasma processes and dry etching are utilized in microelectronics, optics and photonics. Here, we have demonstrated a laser-induced plasma (LIP) etching of single crystalline germanium by an optically pumped reactive plasma, resulting in high quality etching. A Ti:Sapphire laser (λ = 775 nm, EPulse/max. = 1 mJ, t = 150 fs, frep. = 1 kHz) has been used, after focusing with a 60 mm lens, for igniting a temporary plasma in a CF4/O2 gas at near atmospheric pressure. Typical etching rate of approximately ~ 100 nm / min and a surface roughness of less than 11 nm rms were found. The etching results were studied in dependence on laser pulse energy, etching time, and plasma – surface distance. The mechanism of the etching process is expected to be of chemical nature by the formation of volatile products from the chemical reaction of laser plasma activated species with the germanium surface. This proposed laser etching process can provide new processing capabilities of materials for ultra—high precision laser machining of semiconducting materials as can applied for infrared optics machining.

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The relationship between the Young’s modulus and dry etching rate of polydimethylsiloxane (PDMS)

Biomedical Microdevices ◽

10.1007/s10544-019-0379-8 ◽

2019 ◽

Vol 21 (1) ◽

Cited By ~ 5

Author(s):

Matthew L. Fitzgerald ◽

Sara Tsai ◽

Leon M. Bellan ◽

Rebecca Sappington ◽

Yaqiong Xu ◽

...

Keyword(s):

Young’S Modulus ◽

Young's Modulus ◽

Etching Rate ◽

Dry Etching ◽

The Relationship

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Dry Etching of GaN Using Reactive Ion Beam Etching and Chemically Assisted Reactive Ion Beam Etching

MRS Proceedings ◽

10.1557/proc-468-373 ◽

1997 ◽

Vol 468 ◽

Cited By ~ 6

Author(s):

Jae-Won Lee ◽

Hyong-Soo Park ◽

Yong-Jo Park ◽

Myong-Cheol Yoo ◽

Tae-Il Kim ◽

...

Keyword(s):

Room Temperature ◽

Volume Fraction ◽

Ion Beam ◽

Etching Rate ◽

Dry Etching ◽

Ion Beam Etching ◽

Etching Profile ◽

Etching Parameters ◽

Etching Selectivity ◽

Reactive Ion Beam Etching

ABSTRACTDry etching characteristics of GaN using reactive ion beam etching (RIBE) were studied. Etching profile, etching rate and etching selectivity to a photoresist (PR) mask were investigated as a function of various etching parameters. Characteristics of chemically assisted reactive ion beam etching (CARIBE) and RIBE were compared at varied mixtures of CH4 and Cl2. A highly anisotropie etching profile with a smooth surface was obtained for tilted RIBE with Ch at room temperature. Etching selectivity to a PR was dramatically improved in RIBE and CARIBE when a volume fraction of CH4 to the mixture of CH4 and Ch was larger than 0.83.

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A Review: Inductively Coupled Plasma Reactive Ion Etching of Silicon Carbide

Materials ◽

10.3390/ma15010123 ◽

2021 ◽

Vol 15 (1) ◽

pp. 123

Author(s):

Katarzyna Racka-Szmidt ◽

Bartłomiej Stonio ◽

Jarosław Żelazko ◽

Maciej Filipiak ◽

Mariusz Sochacki

Keyword(s):

Silicon Carbide ◽

Inductively Coupled Plasma ◽

Etching Rate ◽

Reactive Ion Etching ◽

Semiconductor Processing ◽

Ion Etching ◽

Inductively Coupled ◽

Hard Materials ◽

Potential Benefits ◽

First Time

The inductively coupled plasma reactive ion etching (ICP-RIE) is a selective dry etching method used in fabrication technology of various semiconductor devices. The etching is used to form non-planar microstructures—trenches or mesa structures, and tilted sidewalls with a controlled angle. The ICP-RIE method combining a high finishing accuracy and reproducibility is excellent for etching hard materials, such as SiC, GaN or diamond. The paper presents a review of silicon carbide etching—principles of the ICP-RIE method, the results of SiC etching and undesired phenomena of the ICP-RIE process are presented. The article includes SEM photos and experimental results obtained from different ICP-RIE processes. The influence of O2 addition to the SF6 plasma as well as the change of both RIE and ICP power on the etching rate of the Cr mask used in processes and on the selectivity of SiC/Cr etching are reported for the first time. SiC is an attractive semiconductor with many excellent properties, that can bring huge potential benefits thorough advances in submicron semiconductor processing technology. Recently, there has been an interest in SiC due to its potential wide application in power electronics, in particular in automotive, renewable energy and rail transport.

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Optimization of piezoelectric MEMS process on Sr and La co-doped PZT thin films

Journal of Advanced Dielectrics ◽

10.1142/s2010135x20500101 ◽

2020 ◽

Vol 10 (04) ◽

pp. 2050010

Author(s):

M. Kathiresan ◽

Jain Jose ◽

E. Varadarajan ◽

R. Ramesh ◽

V. Natarajan ◽

...

Keyword(s):

Thin Film ◽

Thin Films ◽

Lead Zirconate Titanate ◽

Etching Rate ◽

Dry Etching ◽

Mems Devices ◽

Pzt Thin Films ◽

Sensing Applications ◽

Piezoelectric Mems ◽

Co Doped

Doped lead–zirconate–titanate (PZT) thin films are preferred for the development of micro–electro–mechanical systems (MEMS)-based acoustic sensors because of their inherent higher dielectric and piezoelectric coefficients. Patterning process is used to develop such MEMS devices which is highly complex even for undoped PZT thin films; therefore, the problem is further cumbersome for doped PZT thin films due to the presence of added dopant elements and their associated chemistry. This paper presents patterning of strontium (Sr) and lanthanum (La) co-doped PZT thin film (PSLZT) deposited on platinized silicon substrate using wet and dry etching processes for fabricating a diaphragm structure with thickness of 15–25[Formula: see text][Formula: see text]m and diameter of 1.4–2[Formula: see text]mm, suitable for acoustic sensing applications. The effects of various etching conditions have been studied and the results are reported. It is found that the dry etching is the most suited process for realizing the piezoelectric MEMS structure due to its higher etching resolution. An appreciable etching rate of 260–270[Formula: see text]nm/min with smooth vertical sidewalls is achieved. The silicon diaphragm with patterned PSLZT thin film is found to retain more than 80% of its dielectric and piezoelectric coefficients and has a resonance of 1.43[Formula: see text]MHz.

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4H-Silicon Carbide Wafer Surface after Chlorine Trifluoride Gas Etching

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.369 ◽

2018 ◽

Vol 924 ◽

pp. 369-372 ◽

Cited By ~ 1

Author(s):

Shogo Okuyama ◽

Keisuke Kurashima ◽

Ken Nakagomi ◽

Hitoshi Habuka ◽

Yoshinao Takahashi ◽

...

Keyword(s):

Silicon Carbide ◽

Etching Rate ◽

Concentric Circle ◽

Wafer Surface ◽

Deep Etching ◽

Gas Distributor ◽

High Etching Rate ◽

Hole Arrays ◽

Rate Profile ◽

Gas Supply

In order to develop the high etching rate reactor for silicon carbide, the 50-mm-diameter C-face 4H-silicon carbide wafer was etched using the chlorine trifluoride gas at 500 °C. By the deep etching, the concentric-circle-shaped valleys were formed at the positions corresponding to the radii of the pin-hole arrays of the gas distributor, as predicted by the calculation. The etching rate profile of 4H-silicon carbide was concluded to have a relationship with the local chlorine trifluoride gas supply . The wafer bow was small, even the wafer was very thin, about 160 μm thick.

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Development of Silicon Carbide Dry Etcher Using Chlorine Trifluoride Gas

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.738 ◽

2014 ◽

Vol 778-780 ◽

pp. 738-741 ◽

Cited By ~ 7

Author(s):

Dairi Yajima ◽

Hitoshi Habuka ◽

Tomohisa Kato

Keyword(s):

Silicon Carbide ◽

Substrate Temperature ◽

Flow Rate ◽

Substrate Surface ◽

Etching Rate ◽

Numerical Calculations ◽

Total Flow ◽

Total Flow Rate ◽

Gas Concentration ◽

Rate Profile

A SiC dry etching reactor using chlorine trifluoride (ClF3) gas was designed and evaluated with the help of numerical calculations and experimental results. The etching rate was about 16 μm/min when the ClF3 gas concentration, the total flow rate and the SiC substrate temperature were 90%, 0.3 slm and 500 °C, respectively. The gas stream above the substrate surface was concluded to significantly affect the etching rate profile.

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Chlorine Trifluoride Gas Transport and Etching Rate Distribution in Silicon Carbide Dry Etcher

Materials Science Forum ◽

10.4028/www.scientific.net/msf.821-823.553 ◽

2015 ◽

Vol 821-823 ◽

pp. 553-556 ◽

Cited By ~ 8

Author(s):

Dairi Yajima ◽

Ken Nakagomi ◽

Hitoshi Habuka ◽

Tomohisa Kato

Keyword(s):

Silicon Carbide ◽

Gas Transport ◽

Etching Rate ◽

Outer Region ◽

Gas Distribution ◽

Rate Distribution ◽

Gas Distributor ◽

Center Region

A SiC dry etcher using chlorine trifluoride (ClF3) gas was evaluated, particularly about the etching rate distribution. At 100%, the etching rate was high in the center region and was low in the outer region. However, that at 20% showed the opposite profile. This difference was considered to be due to the chlorine trifluoride gas distribution which was built above the gas distributor.

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Planarization of 6-Inch 4H-SiC Wafer Using Catalyst-Referred Etching

Materials Science Forum ◽

10.4028/www.scientific.net/msf.821-823.537 ◽

2015 ◽

Vol 821-823 ◽

pp. 537-540

Author(s):

Ai Isohashi ◽

Yasuhisa Sano ◽

Tomohisa Kato ◽

Kazuto Yamauchi

Keyword(s):

Silicon Carbide ◽

Chemical Etching ◽

Etching Rate ◽

Wafer Surface ◽

Sic Wafer

Catalyst-referred etching (CARE) is a planarization method based on the chemical etching reaction, which does not need abrasives. In this paper, CARE was applied to the planarization of 6-inch silicon carbide (SiC) wafers, and removal properties were investigated. The etching rate was about 20nm/h, which is almost equal to that of 2-inch SiC wafer (16 nm/h). The rms roughness was reduced along with the removal depth, and step-terrace structure was observed in whole area of the on-axis wafer surface.

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Failure Analysis and Process Improvement for Through Silicon Via Interconnects

MRS Proceedings ◽

10.1557/proc-1156-d08-04-f06-04 ◽

2009 ◽

Vol 1156 ◽

Cited By ~ 4

Author(s):

Bivragh Majeed ◽

Marc Van Cauwenberghe ◽

Deniz Sabuncuoglu Tezcan ◽

Philippe Soussan

Keyword(s):

Failure Analysis ◽

Process Improvement ◽

Etching Rate ◽

Dry Etching ◽

Etching Process ◽

Thickness Variation ◽

Silicon Etching ◽

Soft Landing ◽

Etching Profile ◽

Etching Parameters

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

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