A novel method to characterize MOS transistors with mixed gate dielectric technologies

1992 ◽  
Vol 39 (3) ◽  
pp. 734-737 ◽  
Author(s):  
R.R. Siergiej ◽  
M.H. White
Keyword(s):  
Gate Dielectric ◽  
Mos Transistors ◽  
Novel Method

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

scholarly journals Модель термополевой нестабильности p-МОП-транзисторов при отрицательном смещении затвора

2020 ◽  
Vol 54 (2) ◽  
pp. 181
Author(s):  
О.В. Александров
Keyword(s):  
Silicon Substrate ◽  
Gate Dielectric ◽  
Inversion Layer ◽  
Surface States ◽  
Quantitative Model ◽  
Oxide Semiconductor ◽  
Mos Transistors ◽  
Ion Diffusion ◽  
Bias Temperature Instability ◽  
P Type

Abstract A new quantitative model of the negative-bias temperature instability (NBTI) of p -MOS (metal-oxide-semiconductor) transistors is developed. The model is based on the reaction of the depassivation of surface states at the Si–SiO_2 interphase boundary (IPB) and hydrogen-containing hole traps near the Si–SiO_2 IPB by positively charged hydrogen ions H^+, accumulated in the p ^+-type inversion layer of the silicon substrate. The dependences of the surface and space charges in p -MOS transistors on the NBTI time are controlled by the kinetics of H^+-ion diffusion and drift from the silicon substrate to the Si–SiO_2 IPB. The effect of the gate voltage on the NBTI is explained by the effect of the electric-field strength on the H^+ ion segregation coefficient at the Si–SiO_2 IPB. The relaxation of positive space charge introduced into the gate dielectric during NBTI is described by the tunnel discharge of oxide traps by silicon-substrate electrons.

Time to Failure Determination for sub-100 nm MOS Transistors Gate Dielectric by Means of Accelerated Tests

2019 ◽  
Vol 24 (5) ◽  
pp. 469-478
Author(s):  
Alexander S. Sivchenko ◽  
◽  
Evgeny V. Kuznetsov ◽  
Alexander N. Saurov ◽  
◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Time To Failure ◽  
Mos Transistors ◽  
Accelerated Tests

Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors

2020 ◽  
Vol 25 (6) ◽  
pp. 517-524
Author(s):  
D.A. Eliseeva ◽  
◽  
S.O. Safonov ◽  
◽  
Keyword(s):  
Mathematical Models ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Operating Time ◽  
Operating Conditions ◽  
Hole Injection ◽  
Operating Voltage ◽  
Mos Transistors ◽  
The Impact

Nowadays, the developed mathematical models, describing the degradation mechanism of the gate dielectric, permit to determine the value of the operating time to failure of a device depending on its internal properties and operating conditions. These models significantly reduce the time and material required for performing testing and processing of large amounts of experimental data. In the paper the gate dielectric gates based on SiO in n -and p -channel MOS transistors have been studied. It has been found that under the impact of the electric field the degradation of the gate dielectric with 5.3 nm thickness most likely occurs according to the thermochemical model ( E -model) and in case with 7 nm thickness dielectric- in accordance with the anode hole injection model (1/ E -model). The coefficients have been calculated and the analysis of the mathematical models, permitting to determine the service life gate dielectrics based on SiO with 7 nm thickness in n - and p -channel MOS transistors for different values, of their area, operating voltage and temperature, has been performed. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of manufactured MOS transistors.

The Physical Origins of Fast and Slow Components in NBTI Degradation for p-MOS Transistors with SiON Gate Dielectric

2019 ◽  
Vol 6 (3) ◽  
pp. 167-183
Author(s):  
Ming-Fu Li ◽  
Chen Shen ◽  
T Yang ◽  
Gan Chen ◽  
Daming Huang
Keyword(s):  
Gate Dielectric ◽  
Mos Transistors

Novel Stacked CMOS Process by Local Overgrowth

1989 ◽  
Vol 158 ◽  
Author(s):  
René P. Zingg ◽  
B. Hüfflinger ◽  
G. W. Neudeck
Keyword(s):  
Gate Dielectric ◽  
Substrate Material ◽  
Current Drive ◽  
Reverse Order ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Mos Transistors ◽  
Switching Characteristic ◽  
Novel Device ◽  
Channel Region

ABSTRACTA six mask process that yields stacked CMOS circuits is presented. Transistors that were built in reverse order (i. e. the gate first, the gate dielectric second, and only then the channel region) exhibit comparable parameters as conventional devices. A novel device has been built whose current drive is three times that of FETs built in substrate material. The vertical stacking of complementary MOS transistors made it possible to build an inverter with symmetric switching characteristic within the area of a single transistor.

Gate Technology Issues for Silicon Mos Nanotransistors

1999 ◽  
Vol 584 ◽  
Author(s):  
D. M Tennant ◽  
G. L. Timp ◽  
L. E. Ocola ◽  
M. Green ◽  
T. Sorsch ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Ring Structure ◽  
Channel Length ◽  
Low Energy ◽  
Gate Length ◽  
Direct Write ◽  
Mos Transistors ◽  
Processing Elements ◽  
Effective Channel

AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

scholarly journals Modeling and analysis of wavering redistribution of energy in the presence of its own electromagnetic radiation in key electronic circuits on MOS transistors.

2021 ◽  
Author(s):  
K.A. Boikov ◽  
Keyword(s):  
Electromagnetic Radiation ◽  
Gate Dielectric ◽  
Vibrational Energy ◽  
Reference Sample ◽  
Technical Diagnostics ◽  
Mos Transistors ◽  
Modeling And Analysis ◽  
Mos Transistor ◽  
Significant Difference ◽  
Electrical Component

For the first time, a simplified model of the redistribution of vibrational energy in a MOS transistor has been developed and analyzed. The transistor is turned on in open drain mode and in inverter mode. After calculating the parameters, the numerical radio profiles of the signals of the electrical component of electromagnetic radiation, created by the key unit itself, were obtained. An experiment was carried out to register the vibrational redistribution of energy in a MOS transistor using a specially designed sample. The results of registration of a series of radio profiles of signals with the configuration of the universal ports of the sample of a digital device are presented, and a correlation assessment of the reproducibility of the experiment is carried out. The correlation of the radio profiles of the signals obtained as a result of modeling and as a result of the experiment is not lower than 0.93. This testifies to the correctness of the developed models. On the basis of the presented development, a correlation assessment of the radiation of a reference sample and a sample with a slight deviation of parameters has been carried out. Even with a slight change in the parameters of the key node associated with degradation of the gate dielectric, the cross-correlation in the normal state and with a defect r < 0.7, which indicates a significant difference in the signal radio profile of normal functioning and with deterioration of parameters. The proposed models can be used in passive radio-wave technical diagnostics based on the registration of the electrical component of electromagnetic radiation generated by the radio-electronic devices themselves and opens up new possibilities for diagnosing malfunctions at the early stages of their occurrence.

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