Novel Stacked CMOS Process by Local Overgrowth

1989 ◽  
Vol 158 ◽  
Author(s):  
René P. Zingg ◽  
B. Hüfflinger ◽  
G. W. Neudeck
Keyword(s):  
Gate Dielectric ◽  
Substrate Material ◽  
Current Drive ◽  
Reverse Order ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Mos Transistors ◽  
Switching Characteristic ◽  
Novel Device ◽  
Channel Region

ABSTRACTA six mask process that yields stacked CMOS circuits is presented. Transistors that were built in reverse order (i. e. the gate first, the gate dielectric second, and only then the channel region) exhibit comparable parameters as conventional devices. A novel device has been built whose current drive is three times that of FETs built in substrate material. The vertical stacking of complementary MOS transistors made it possible to build an inverter with symmetric switching characteristic within the area of a single transistor.

scholarly journals A Study on the Variable Inductor Design by Switching the Main Paths and the Coupling Coils

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1856
Author(s):  
Yen-Chung Chiang ◽  
Juo-Chen Chen ◽  
Yu-Hsin Chang
Keyword(s):  
Design Method ◽  
The Other ◽  
Cmos Process ◽  
Mos Transistors ◽  
Quality Factors ◽  
Process Technology ◽  
Variation Versus ◽  
Variable Inductor ◽  
Metal Layers ◽  
Coupled Coils

In a radio frequency (RF) system, it is possible to use variable inductors for providing tunable or selective frequency range. Variable inductors can be implemented by the microelectromechanical system (MEMS) process or by using transistors as switches to change the routing of coils or coupling quantities. In this paper, we investigated the design method of a variable inductor by using MOS transistors to switch the main coil paths and the secondary coupled coils. We observed the effects of different metal layers, turn numbers, and layout arrangements for secondary-coupled coils and compared their characteristics on the inductances and quality factors. We implemented two chips in the 0.18 m CMOS process technology for each kind of arrangement for verification. One inductor can achieve inductance values from about 300 pH to 550 pH, and the other is between 300 pH and 575 pH, corresponding to 59.3% and 62.5%, respectively, inductance variation range at 4 GHz frequency. Additionally, their fine step sizes of the switched inductances are from 0.5% to 6% for one design, and 1% to 12.5% for the other. We found that both designs achieved a large inductance tuning range and moderate inductance step sizes with a slight difference behavior on the inductance variation versus frequency.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

MILLIMETER WAVE TO TERAHERTZ IN CMOS

2009 ◽  
Vol 19 (01) ◽  
pp. 55-67 ◽  
Author(s):  
K. K. O ◽  
S. SANKARAN ◽  
C. CAO ◽  
E.-Y. SEOK ◽  
D. SHIM ◽  
...  
Keyword(s):  
Output Power ◽  
Millimeter Wave ◽  
Fundamental Mode ◽  
Cmos Circuits ◽  
Noise Performance ◽  
Mos Transistors

The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.

scholarly journals Minimum MOS Transistor Count Fractional-Order Voltage-Mode and Current-Mode Filters

Technologies ◽  
2019 ◽  
Vol 7 (4) ◽  
pp. 85
Author(s):  
Panagiotis Bertsias ◽  
Costas Psychalinos ◽  
Ahmed S. Elwakil ◽  
Brent Maundy
Keyword(s):  
Fractional Order ◽  
Transfer Functions ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Process ◽  
Mos Transistors ◽  
Correct Operation ◽  
Mos Transistor ◽  
Voltage Mode ◽  
Filter Structures

Voltage-mode and current-mode fractional-order filter topologies, which are capable of realizing various types of transfer functions, are introduced in this paper. Thanks to the employment of the transconductance parameter of the MOS transistors, the derived filter structures offer the benefit of the electronic adjustment of their frequency characteristics. With regards to the literature, the number of MOS transisitors is minimized leading to significant reduction of the circuit complexity and power dissipation. Simulation results, derived using the Design Kit of the 0.35 μm Austria Mikro Systeme CMOS process and the Cadence IC design suite, confirm the correct operation of the presented filter structures.

Physical characterization of HfO2deposited on Ge substrates by MOCVD.

2004 ◽  
Vol 811 ◽  
Author(s):  
S. Van Elshocht ◽  
B. Brijs ◽  
M. Caymax ◽  
T. Conard ◽  
S. De Gendt ◽  
...  
Keyword(s):  
Physical Properties ◽  
Gate Dielectric ◽  
Substrate Material ◽  
Silicon Substrates ◽  
Enabling Technology ◽  
The Past ◽  
High K ◽  
Alternative Approach ◽  
Made In

ABSTRACTGermanium is because of its intrinsically higher mobility than Si, currently under consideration as an alternative approach to improve transistor performance. Germanium oxide, however, is thermodynamically unstable, preventing formation of the gate dielectric by simple oxidation. At present, high-k dielectrics might be considered as an enabling technology as much progress has been made in the deposition of thin high-quality layers.In this paper, we study the growth and physical properties of HfO2 deposited on Ge by MOCVD, using TDEAH and O2 as precursors, and compare the results to similar layers deposited on silicon substrates. Our results show that the physical properties of MOCVD-deposited HfO2 layers on Ge are very similar to what we have observed in the past for Si. Unfortunately, some of the negative aspects observed for Si, such as diffusion of substrate material in the high-k layer, a low density for thinner layers, or a rough top surface, are also observed for the case of Ge. However, careful surface pretreatments such as NH3 annealing the Ge substrate prior to deposition, can greatly improve the physical properties. An important observation is the very thin interfacial layer between HfO2 and Ge substrate, allowing a more aggressive scaling for Ge.

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

2001 ◽  
Vol 670 ◽  
Author(s):  
Avinash Agarwal ◽  
Michael Freiler ◽  
Pat Lysaght ◽  
Loyd Perrymore ◽  
Renate Bergmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Film ◽  
Cmos Process ◽  
Gate Stack ◽  
Process Flow ◽  
High K ◽  
High K Materials ◽  
Wet Etch ◽  
The Impact ◽  
High K Gate Dielectric

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

An Improved CAL Register File with Dual-Threshold Technique for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 186-191 ◽  
Author(s):  
Jian Ping Hu ◽  
Jia Guo Zhu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Total Power ◽  
Cmos Process ◽  
Register File ◽  
Mos Transistors ◽  
Leakage Currents ◽  
Micro Power ◽  
Scaling Down ◽  
Threshold Technique

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.

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