Analytical model to study temperature dependent Negative Capacitance effect on long channel Double Gate Ferroelectric Junctionless Transistor

2016 Asia-Pacific Microwave Conference (APMC) ◽

10.1109/apmc.2016.7931309 ◽

2016 ◽

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Analytical Model ◽

Negative Capacitance ◽

Double Gate ◽

Temperature Dependent ◽

Capacitance Effect ◽

Junctionless Transistor ◽

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Impact of High-k spacer and Negative Capacitance on Double Gate Junctionless Transistor for Improved Short Channel Immunity and Reliability

2018 4th International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2018.8605167 ◽

2018 ◽

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Negative Capacitance ◽

Double Gate ◽

Short Channel ◽

High K ◽

Junctionless Transistor

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Impact of Gaussian Doping Profile and Negative Capacitance Effect on Double-Gate Junctionless Transistors (DGJLTs)

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2832843 ◽

2018 ◽

Vol 65 (7) ◽

pp. 2699-2706 ◽

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Doping Profile ◽

Negative Capacitance ◽

Double Gate ◽

Capacitance Effect ◽

Junctionless Transistors

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Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

Silicon ◽

10.1007/s12633-019-00280-9 ◽

2019 ◽

Vol 12 (9) ◽

pp. 2053-2063 ◽

Author(s):

S. Manikandan ◽

N. B. Balamurugan ◽

D. Nirmal

Keyword(s):

Low Power ◽

Analytical Model ◽

Double Gate ◽

Junctionless Transistor

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An analytical model for long channel Double Gate Ge Ferroelectric FET (DGGeFeFET) to study the impact of interface trap charges

2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon) ◽

10.1109/smarttechcon.2017.8358506 ◽

2017 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Analytical Model ◽

Interface Trap ◽

Double Gate ◽

Long Channel ◽

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Superior Performance and Reliability of Double Gate Gaussian Doped Negative Capacitance Junctionless Transistor for 200–500 K

IETE Technical Review ◽

10.1080/02564602.2019.1642149 ◽

2019 ◽

Vol 37 (4) ◽

pp. 391-401

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Superior Performance ◽

Negative Capacitance ◽

Double Gate ◽

Junctionless Transistor

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Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

Journal of Semiconductors ◽

10.1088/1674-4926/39/10/104004 ◽

2018 ◽

Vol 39 (10) ◽

pp. 104004

Author(s):

Huifang Xu

Keyword(s):

Analytical Model ◽

Field Effect ◽

Field Effect Transistor ◽

Gate Dielectric ◽

Negative Capacitance ◽

Double Gate ◽

Two Dimensional ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect Transistor

Silicon ◽

10.1007/s12633-020-00643-7 ◽

2020 ◽

Author(s):

Yibiao Dong ◽

Ru Han ◽

Danghui Wang ◽

Ruofei Wang ◽

Chenmeng Guo

Keyword(s):

Analytical Model ◽

Temperature Effects ◽

Field Effect ◽

Field Effect Transistor ◽

Negative Capacitance ◽

Double Gate ◽

Interface Traps ◽

Effect Transistor

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Analytical drain current model for long-channel double-gate negative capacitance junctionless transistors using Landau theory

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2016.7785204 ◽

2016 ◽

Author(s):

Chunsheng Jiang ◽

Renrong Liang ◽

Jing Wang ◽

Jun Xu

Keyword(s):

Landau Theory ◽

Current Model ◽

Drain Current ◽

Negative Capacitance ◽

Double Gate ◽

Junctionless Transistors ◽

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Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges

Superlattices and Microstructures ◽

10.1016/j.spmi.2018.03.001 ◽

2018 ◽

Vol 117 ◽

pp. 189-199 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Interface Trap ◽

Negative Capacitance ◽

Double Gate ◽

Capacitance Effect ◽

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Analysis of Negative Capacitance Double-Gate Junctionless Transistor for the Variation of Device Parameters

Lecture Notes in Electrical Engineering - Recent Trends in Electronics and Communication ◽

10.1007/978-981-16-2761-3_24 ◽

2021 ◽

pp. 255-262

Author(s):

Manish Kumar Rai ◽

Sanjeev Rai

Keyword(s):

Negative Capacitance ◽

Double Gate ◽

Junctionless Transistor

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