A Novel Design of Quantum 3:8 Decoder Circuit using Reversible Logic for Improvement in Key Quantum Circuit Design Parameters

2021 ◽  
Author(s):  
Seyyed Mohammad Amir Mirizadeh ◽  
Mohammad Mahdi Emadi Kouchak ◽  
Mohammad Mahdi Panahi
Keyword(s):  
Circuit Design ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Design Parameters ◽  
Novel Design ◽  
Decoder Circuit

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

2019 ◽  
Vol 28 (05) ◽  
pp. 1950079 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghanekar
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
High Performance ◽  
Single Layer ◽  
Memory Cell ◽  
Design Parameters ◽  
Flip Flop ◽  
Negative Edge ◽  
Wire Crossing ◽  
The Common

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

scholarly journals Mathematical formulation of quantum circuit design problems in networks of quantum computers

2020 ◽  
Vol 19 (5) ◽  
Author(s):  
R. van Houte ◽  
J. Mulderij ◽  
T. Attema ◽  
I. Chiscop ◽  
F. Phillipson
Keyword(s):  
Circuit Design ◽  
Mathematical Formulation ◽  
Quantum Circuit ◽  
Quantum Computers ◽  
Design Problems

scholarly journals Symmetric stacked fast binary counters based on reversible logic

2018 ◽  
Vol 7 (4) ◽  
pp. 2747
Author(s):  
C Santhi ◽  
Dr. Moparthy Gurunadha Babu
Keyword(s):  
Energy Dissipation ◽  
Circuit Design ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
Logic Gates ◽  
Digital Circuit ◽  
Information Loss ◽  
Reversible Logic ◽  
Binary Counter ◽  
Reversible Logic Gates

A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit. 

scholarly journals Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Naser Mohammadzadeh ◽  
Tayebeh Bahreini ◽  
Hossein Badri
Keyword(s):  
Circuit Design ◽  
Design Methodology ◽  
Ion Trap ◽  
Quantum Circuit ◽  
Physical Design ◽  
Quantum Circuits ◽  
Mixed Integer ◽  
Routing And Scheduling ◽  
Design And Synthesis ◽  
Proposed Model

Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The proposed model which is a mixed integer linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms of latency. Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks.

Multiple path generation by a flexible four-bar mechanism using ionic polymer metal composite

2012 ◽  
Vol 23 (12) ◽  
pp. 1379-1393 ◽  
Author(s):  
Ravi K Jain ◽  
Somajoyti Majumder ◽  
Ashish Dutta
Keyword(s):  
Bending Moment ◽  
Design Parameters ◽  
Metal Composite ◽  
Ionic Polymer Metal Composite ◽  
Ionic Polymer ◽  
Adams Software ◽  
Multiple Paths ◽  
Polymer Metal ◽  
Simulation Results ◽  
Novel Design

This article presents a novel design of a flexible four-bar crank–rocker mechanism using ionic polymer metal composite for generating multiple paths, which can be applied in microassembly. In order to control the deflection of links and the resultant path, active ionic polymer metal composite patches are fixed on the coupler and are actuated by a voltage (0–3 V direct current). The main focus of this article is to determine the number, size, and location of the ionic polymer metal composite patches to be used on the coupler to get a desired path. A dynamic model of the mechanism is made in ADAMS software and the design parameters are identified. A mathematical model of ionic polymer metal composite patch is developed through experiments to achieve the bending moment relationship with voltage, and this is used while simulating its behaviors. The simulation results show that the proposed mechanism can generate multiple paths, using different voltages for ionic polymer metal composite activation. The proposed mechanism is then fabricated, and experiments are carried out to compare the experimental and simulation results. It is proved that the proposed new mechanism is superior to earlier designs of four bars using ionic polymer metal composite, and the paths generated can more effectively be controlled.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650076 ◽  
Author(s):  
Praveena Murugesan ◽  
Thanushkodi Keppanagounder ◽  
Vijeyakumar Natarajan
Keyword(s):  
Critical Role ◽  
Optical Computing ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Submicron ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Single Digit ◽  
Gate Count ◽  
Ripple Carry Adder ◽  
Novel Design

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

Sign in / Sign up

Export Citation Format

Share Document