Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650076 ◽  
Author(s):  
Praveena Murugesan ◽  
Thanushkodi Keppanagounder ◽  
Vijeyakumar Natarajan
Keyword(s):  
Critical Role ◽  
Optical Computing ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Submicron ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Single Digit ◽  
Gate Count ◽  
Ripple Carry Adder ◽  
Novel Design

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

A Bio-inspired and Low-power 2D Machine Vision with Adaptive Machine Learning and Forgetting

2021 ◽  
Author(s):  
Akhil Dodda ◽  
Darsith Jayachandran ◽  
Shiva Subbulakshmi Radhakrishnan ◽  
Saptarshi Das
Keyword(s):  
Machine Vision ◽  
Energy Gap ◽  
Critical Role ◽  
Visual Stimuli ◽  
Bright Light ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Role ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Large Area

Abstract Natural intelligence has many dimensions, and in animals, learning about the environment and making behavioral changes are some of its manifestations. In primates vision plays a critical role in learning. The underlying biological neural networks contain specialized neurons and synapses which not only sense and process the visual stimuli but also learns and adapts, with remarkable energy efficiency. Forgetting also plays an active role in learning. Mimicking the adaptive neurobiological mechanisms for seeing, learning, and forgetting can, therefore, accelerate the development of artificial intelligence (AI) and bridge the massive energy gap that exists between AI and biological intelligence. Here we demonstrate a bio-inspired machine vision based on large area grown monolayer 2D phototransistor array integrated with analog, non-volatile, and programmable memory gate-stack that not only enables direct learning, and unsupervised relearning from the visual stimuli but also offers learning adaptability under photopic (bright-light), scotopic (low-light), as well as noisy illumination conditions at miniscule energy expenditure. In short, our “all-in-one” hardware vision platform combines “sensing”, “computing” and “storage” not only to overcome the von Neumann bottleneck of conventional complementary metal oxide semiconductor (CMOS) technology but also to eliminate the need for peripheral circuits and sensors.

scholarly journals Optical Design of Compact Space Autonomous Docking Instrument with CMOS Image Sensor and All Radiation Resistant Lens Elements

2020 ◽  
Vol 10 (15) ◽  
pp. 5302
Author(s):  
Sheng-Feng Lin ◽  
Cheng-Huan Chen
Keyword(s):  
Optical Glass ◽  
Optical Design ◽  
Critical Role ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Space Vehicles ◽  
Glass Material ◽  
Radiation Resistant ◽  
Autonomous Docking

Built-in autonomous stereo vision devices play a critical role in the autonomous docking instruments of space vehicles. Traditional stereo cameras for space autonomous docking use charge-coupled device (CCD) image sensors, and it is difficult for the overall size to be reduced due to the size of the CCD. In addition, only the few outermost elements of the camera lens use radiation-resistant optical glass material. In this paper, a complementary metal–oxide semiconductor (CMOS) device is used as the image sensor, and radiation-resistant optical glass material is introduced to all lens elements in order to make a compact and highly reliable space grade instrument. Despite the limited available material, a fixed focus module with 7 lens elements and overall length of 42 mm has been achieved, while meeting all the required performance demands for the final vision-guided docking process.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

scholarly journals Novel Techniques for Noise-Tolerance in Combinational Critical-Path Circuit Components

2020 ◽  
Vol 9 (4) ◽  
pp. 636-639
Keyword(s):  
Large Scale ◽  
Critical Path ◽  
Vlsi Design ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Flip Flop ◽  
Path Component ◽  
Circuit Components ◽  
New Research

The continued scaling of the device and interconnect in the deep submicron jurisdiction of the complementary metal oxide semiconductor (CMOS) very large scale design (VLSI) has brought many new design challenges and exposed the limitations of the traditional VLSI design. One of the most severe problems in the deep submicron is that the circuit tend to malfunction by producing incorrect outputs in the event of inputs that have glitch. Such noise problem has emerged as the critical reliability problem in the deep submicron, in addition to the power dissipation problem. In this proposal, new research is proposed to counter the noise problem through novel circuit design techniques and methodologies. As we continue in deep submicron, the reliability of such designs is reduced as the output levels of such circuit suffer because of voltage scaling. We present our research along with the results and then describe the further proposed research. The research techniques are described using the combinatorial gates which serve as the critical path component in many designs. Also, an efficient flip-flop CD, that is conditionally discharged when there is no input changes and the input remains high to high, is proposed. This new flip-flop reduces the switching state activity, and is almost glitch-less at the output. The results from our proposed techniques demonstrate at least 2.3x the noise-immunity over the best known results in the literature.

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