A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology

Author(s):  
Michal Wolodzko ◽  
Wieslaw Kuzmicz
2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.


2015 ◽  
Vol 91 (5) ◽  
pp. 1485-1492 ◽  
Author(s):  
Karen Gómez-Pazarín ◽  
Celia Flores ◽  
Tania Castillo ◽  
Jochen Büchs ◽  
Enrique Galindo ◽  
...  

2012 ◽  
Vol 2012 (1) ◽  
pp. 000018-000022
Author(s):  
S.Q. Gu ◽  
D.W. King ◽  
V. Ramachandran ◽  
B. Henderson ◽  
U. Ray ◽  
...  

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.


Author(s):  
V. Issakov ◽  
R. Ciocoveanu ◽  
R. Weigel ◽  
A. Geiselbrechtinger ◽  
J. Rimmelspacher
Keyword(s):  
60 Ghz ◽  

2019 ◽  
Vol 54 (1) ◽  
pp. 6-17 ◽  
Author(s):  
Emanuele Depaoli ◽  
Hongyang Zhang ◽  
Marco Mazzini ◽  
Walter Audoglio ◽  
Augusto Andrea Rossi ◽  
...  
Keyword(s):  

Author(s):  
Johannes Rimmelspacher ◽  
Radu Ciocoveanu ◽  
Giovanni Steffan ◽  
Matteo Bassi ◽  
Vadim Issakov

Sensors ◽  
2020 ◽  
Vol 20 (21) ◽  
pp. 6156
Author(s):  
Fernando Moreno-Cruz ◽  
Víctor Toral-López ◽  
Antonio Escobar-Molero ◽  
Víctor U. Ruíz ◽  
Almudena Rivadeneyra ◽  
...  

Although the number of Internet of Things devices increases every year, efforts to decrease hardware energy demands and to improve efficiencies of the energy-harvesting stages have reached an ultra-low power level. However, no current standard of wireless communication protocol (WCP) can fully address those scenarios. Our focus in this paper is to introduce treNch, a novel WCP implementing the cross-layer principle to use the power input for adapting its operation in a dynamic manner that goes from pure best-effort to nearly real time. Together with the energy-management algorithm, it operates with asynchronous transmissions, synchronous and optional receptions, short frame sizes and a light architecture that gives control to the nodes. These features make treNch an optimal option for wireless sensor networks with ultra-low power demands and severe energy fluctuations. We demonstrate through a comparison with different modes of Bluetooth Low Energy (BLE) a decrease of the power consumption in 1 to 2 orders of magnitude for different scenarios at equal quality of service. Moreover, we propose some security optimizations, such as shorter over-the-air counters, to reduce the packet overhead without decreasing the security level. Finally, we discuss other features aside of the energy needs, such as latency, reliability or topology, brought again against BLE.


Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.


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