An output-capacitor-less low-dropout voltage regulator with high power supply rejection ratio and fast load transient response using boosted-input-transconductance structure

2015 ◽  
Author(s):  
Hao Luo ◽  
Liter Siek
Keyword(s):  
Transient Response ◽  
High Power ◽  
Power Supply ◽  
Voltage Regulator ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Output Capacitor ◽  
Supply Rejection

An Improved Bandgap Reference with Curvature-Compensated and High Power Supply Rejection

2016 ◽  
Vol 25 (11) ◽  
pp. 1650147 ◽  
Author(s):  
Hongbing Wu ◽  
Hongxia Liu
Keyword(s):  
High Power ◽  
Power Supply ◽  
Low Frequency ◽  
Bandgap Reference ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Resistor String ◽  
Typical Condition ◽  
Active Design ◽  
Supply Rejection

This paper presents a bandgap reference (BGR) with the characteristics of curvature-compensation and high power supply rejection ratio (PSRR). To achieve a better performance, the base current of BJT is injected to a small segment of resistor string to flatten the temperature variation, and a pre-regulator of the power supply is implemented to improve the PSRR. The circuits, designed in 0.18[Formula: see text][Formula: see text]m BCD technology, exhibit an average voltage of 1.212[Formula: see text]V with temperature coefficient of 2.0[Formula: see text]ppm/[Formula: see text] in the range from [Formula: see text] to 110[Formula: see text] at typical condition, and a power supply rejection ratio of [Formula: see text][Formula: see text]dB at low frequency. After 4-bit trimming, Monte Carlo simulation results show that the proposed design gets an accuracy of 0.29%, with a variation of [Formula: see text][Formula: see text]mV. The active design area is 160[Formula: see text][Formula: see text]m, and the power supply current is about 8.2[Formula: see text][Formula: see text]A.

Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach

2019 ◽  
Vol 17 (10) ◽  
pp. 777-783
Author(s):  
Shishu Pal ◽  
Ashutosh Nandi
Keyword(s):  
High Power ◽  
Power Supply ◽  
Circuit Simulation ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Supply Rejection

This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for start-up circuit. The measured settling time for output reference voltage is observed to be less than 4 μs. No filtering capacitor is used to improve the PSRR, which is –97 dB up to 1 MHz and subsequently reduces to –47.5 dB at 158 MHz.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

scholarly journals A Transient-Enhanced Voltage Regulator with Stability and Power-Supply-Rejection Boosting

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Yue Shi ◽  
Anqi Wang ◽  
Jianwen Cao ◽  
Zekun Zhou
Keyword(s):  
Power Supply ◽  
Low Voltage ◽  
Input Voltage ◽  
Voltage Regulator ◽  
Load Range ◽  
Load Regulation ◽  
The Stability ◽  
Output Capacitor ◽  
Better Than ◽  
Supply Rejection

AbstractA high-stability voltage regulator (VR) is proposed in this paper, which integrates transient enhancement and overcurrent protection (OCP). Taken into consideration the performance and area advantages of low-voltage devices, most control parts of proposed VR are supplied by the regulated output voltage, which forms self-power technique (SPT) with power supply rejection (PSR) boosting. Besides, the stability and transient response are enhanced by dynamic load technique (DLT). An embedded overcurrent feedback loop is also adopted to protect the presented VR from damage under overload situations. The proposed VR is implemented in a standard 350 nm BCD technology, whose results indicate the VR can steadily work with 5.5–30 V input voltage, 0–30 mA load range, and 0.1–3.3 μF output capacitor. A 2.98 μV/V line regulation and a 0.233 mV/mA load regulation are achieved with a 40 mA current limiting. The PSR is better than − 64 dB up to 10 MHz with a 0.1 μF output capacitor.

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