Hygro-thermo-mechanical modeling of mixed flip-chip and wire bond stacked die BGA module with molded underfill

Author(s):  
Xueren Zhang ◽  
Tong Yan Tee ◽  
Hun Shen Ng ◽  
J. Teysseyre ◽  
S. Loo ◽  
...  
Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.


Author(s):  
Tan Hua Hong ◽  
John Beleran ◽  
Koh Y. S. Drake ◽  
Ong P. L. Wilson ◽  
Gaurav Mehta ◽  
...  
Keyword(s):  

2020 ◽  
Vol 13 (5s) ◽  
pp. 105-109
Author(s):  
С.А. Региня ◽  
Н.Ю. Ершова ◽  
П.В. Луньков
Keyword(s):  

Рассмотрена гибридная технология производства микросборок с одновременным применением технологий Flip-Chip и Wire Bond, отрабатываемая на предприятии индустриального партнера GS Nanotech. Описаны особенности основных технологических операций и методов контроля качества на каждом этапе производства.


Author(s):  
Chee Meng Chai ◽  
Stephan Stoeckl ◽  
Heinz Pape ◽  
Foo Mun Yee ◽  
Tan Ai Min

2013 ◽  
Vol 52 (1) ◽  
pp. 731-734
Author(s):  
S. Pan ◽  
K. Li ◽  
S. Dang ◽  
X. L. Chen ◽  
Y. Zhang ◽  
...  
Keyword(s):  

2019 ◽  
Vol 2019 (1) ◽  
pp. 000100-000102
Author(s):  
Bong Rosario ◽  
Joseph Holyoak ◽  
Mohsen Haji-Rahim ◽  
Gene Lambird ◽  
Yong Wang ◽  
...  

Abstract Cu pillar flip-chip die technology has proved reliable and is widely used in chip-to-package mobile module products. There was a time when customers considered 500ppm (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50ppm. This high customer expectation drove this in-depth research and problem solve. Our main work includes: 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE) and ultimately improved yield.


2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.


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