Evaluation and optimization of die-shift in Embedded Wafer-Level Packaging by enhancing the adhesion strength of silicon chips to carrier wafer

2011 ◽  
Author(s):  
J. Mazuir ◽  
V. Olmeta ◽  
M. Yin ◽  
G. Pares ◽  
A. Planchais ◽  
...  
Keyword(s):  
Adhesion Strength ◽  
Wafer Level ◽  
Silicon Chips ◽  
Wafer Level Packaging ◽  
Carrier Wafer

Integrated Microsystems

2012 ◽  
Vol 81 ◽  
pp. 55-64 ◽  
Author(s):  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wireless Systems ◽  
Tactile Sensor ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Silicon Chips ◽  
Open Collaboration ◽  
Wafer Level Packaging ◽  
Integrated Microsystems ◽  
Safety Systems ◽  
The Cost

Technology called MEMS (Micro Electro Mechanical Systems) or microsystems are heterogeneous integration on silicon chips and play important roles as sensors. MEMS as switches and resonators fabricated on LSI are needed for future multi-band wireless systems. MEMS for safety systems as event driven tactile sensor network for nursing robot are developed. Wafer level packaging for MEMS and open collaboration to reduce the cost for the development are discussed.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

scholarly journals Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing System ◽  
Grey System Theory ◽  
Grey Model ◽  
Grey System ◽  
Wafer Level ◽  
Short Term ◽  
Packaging Process ◽  
Wafer Level Packaging

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

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