Abstract
As the final step of IC fabrication, packaging is the process to encapsulate the chip and provide the interconnections for the I/O of the final form factor. The demand for increasingly higher I/O density, shrinking device size and lower cost that drive wafer processing also apply to the packaging process. Various technologies have been developed in order to achieve these goals with most of them being wafer-level packaging (WLP). Unlike traditional packaging process, most I/O interconnections are done at the wafer-level with redistribution layers (RDLs). RDLs are the layer where copper lines and vias form the electrical connections. Depending on the applications' market such as mobile, memory or the Internet of Things (IoT), fan-out wafer level packaging (FOWLP) provides the most promising method to support the I/O density requirements and fine RDL line/space. Moreover, fan-out panel level packaging (FOPLP) was also developed in order to capitalize on economies of scale and optimize substrate utilization. In this technology, a rectangular substrate is used in the process instead of a round-shape substrate like a wafer.
Processes and equipment have long been developed for the wafer substrate market, but the previous developments cannot be directly applied to panel substrates. For instance, in the wafer line, spin on processes are very prevalent but these are not at all practical for a panel line. Some capital equipment manufacturers have been reluctant to embrace panel-level manufacturing due to the uncertainty as to whether it will prevail. Struggles with yield have been very common; some of which are due to die placement and others due to the lack of process control capabilities. With the explosion and adoption of FOWLP to enhance package shrinkage and performance the panel market becomes more and more viable. The companies that have embraced panel level manufacturing from the beginning have a distinct advantage due to their intimate knowledge and experience with the substrates as well as the relationship developed with capital equipment suppliers to develop the necessary technology in order to process the panels. However, there is still a great need to ensure the product mix deployed in panel form can have an acceptable yield; automated optical inspection and die placement metrology bridge that gap.
Automated optical inspection allows for defect detection with traditional bright field (BF) or dark field (DF) illumination and also a new novel illumination technique that enables the detection of organic particles and/or residues that are often used in panel-level packaging processes. A system capable of macro defect detection with sub-micron capabilities allows for multi-purpose panel inspections. The system is also equipped with metrology capabilities for critical dimension and die placement measurements which meet the process node dimensional requirements. These features allow for process control of pick and place, overlay as well as feed-forward capabilities for die placement corrections.
In a FOWLP/FOPLP process, chip first and chip last can be concluded among all available methods in the market. Die placement either start from the initial phase of the process or in the final phase of the process. In the chip first scenario, the chips are placed on a carrier by a pick-and-place system and then followed by an encapsulating molding process to reconstitute a substrate (reconstituted wafer or reconstituted panel). At this point a semi-additive process (SAP) is typically followed which includes a photo resist layer being coated, exposed and developed following copper (Cu) plating in order to form the redistribution layer. In this workflow, the die position are dominated by the accuracy of the pick-and-place tool and coefficient of thermal expansion (CTE) mismatch of the molding material and carrier. The trade-off between throughputs, placement accuracy and a feedback mechanism is the main impact from the pick-and-place tool in this process step. This affects both the chip first and chip last scenarios. The thermal expansion of the molding process not only adds additional die shift but also causes warpage of the reconstituted substrate that becomes an issue for automated handling systems and local process variation.
Therefore, to know the actual die position and orientation after the die placement and molding process is crucial for matching with the following redistribution layers development. In one scenario it is possible to utilize the lithography system to perform die position metrology, however, this is time consuming and impacts the cost of ownership and overall throughput for the lithography process. A solution to this problem is provided by implementation of an optical metrology system. Since this information needs to be passed to the lithography tool in a usable manner for variable exposure positioning, the alignment of the stage coordinate system between the die metrology tool and lithography tool is a key point to ensure the correctness of the feed forward loop. For RDL development overlay between die and RDL via directly impact yield and are just as critical to the process as defect inspection and critical dimension measurements. Based on the corrections for each die, a yield prediction can be made and provides different strategies for the lithography tool's exposure field in order to balance throughput and exposure yield rate.
In this paper, we demonstrate a solution using an automatic optical inspection (AOI) system to perform the die metrology for chip placement and RDL development in FOPLP and FOWLP. This includes die shift, die rotation, RDL inspection as well as the overlap between a reconstituted substrate and RDLs. This solution provides comprehensive coverage for packaging process control and significantly impacts yield optimization and throughput enhancement. With a multifunctional AOI system, it also reduces the cost of ownership for packaging processes.
