Localization of Hotspots from Lock-in Thermography Images for Failure Analysis

2021 ◽  
Author(s):  
Rui Zhen Tan ◽  
Neelakantam Venkatarayalu ◽  
Zhongqiang Ding ◽  
Indriyati Atmosukarto ◽  
A. B. Premkumar ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Lock In

Accurate Defect Localization of Stacked Die Devices by Lock-in Thermography

2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang
Keyword(s):  
Failure Analysis ◽  
Defect Modes ◽  
Defect Localization ◽  
Lock In

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

scholarly journals Infrared Thermography applied to power electron devices investigation

2015 ◽  
Vol 28 (2) ◽  
pp. 205-212 ◽  
Author(s):  
Giovanni Breglio ◽  
Andrea Irace ◽  
Luca Maresca ◽  
Michele Riccio ◽  
Gianpaolo Romano ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Infrared Thermography ◽  
Semiconductor Devices ◽  
Electronic Devices ◽  
Experimental Characterization ◽  
Ir Thermography ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Electron Devices ◽  
Lock In

The aim of this paper is to give a presentation of the principal applications of Infrared Thermography for analysis and testing of electrondevices. Even though experimental characterization could be carried out on almost any electronic devices and circuits, here IR Thermography for investigation of power semiconductor devices is presented. Different examples of functional and failure analysis in both transient and lock-in modes will be reported.

Creative Approach Using Lock-in Thermography in Fault Localization of ASIC Devices

2018 ◽  
Author(s):  
Andrew Sabate ◽  
Rommel Estores
Keyword(s):  
Low Power ◽  
Failure Analysis ◽  
Thermal Imaging ◽  
Fault Localization ◽  
Thermal Activity ◽  
Root Cause ◽  
Material Preparations ◽  
Imaging Application ◽  
Set Up ◽  
Lock In

Abstract The advent of lock-in thermal imaging application on semiconductor failure analysis added capability to localize failures through thermal activity (emission) of the die. When coupled with creative electrical set-up and material preparations, lock-in thermography (LIT) [1, 2] application gives more possibility in exploring the failure of the device using low power settings. This gives higher probability of preserving the defect which leads to a more conclusive root cause determination.

Lock-in Thermography for Flip-Chip Package Failure Analysis

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Jeffery Huynh ◽  
Joseph Tan ◽  
Meng-Yeow Tay ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Flip Chip ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Lock In

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Scan Chain Debug Using Dynamic Lock-In Thermography

2011 ◽  
Author(s):  
L. Forli ◽  
B. Picart ◽  
A. Reverdy ◽  
R. Schlangen
Keyword(s):  
Failure Analysis ◽  
Efficient Solution ◽  
Use Cases ◽  
Thermal System ◽  
Complementary Technique ◽  
Scan Chain ◽  
Lock In

Abstract In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.

Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator

2017 ◽  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan
Keyword(s):  
Heat Source ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
System Level ◽  
Thermal Failure ◽  
Analysis Process ◽  
Lock In

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator

Enhanced Failure Analysis on Open TSV Interconnects

2012 ◽  
Author(s):  
F. Altmann ◽  
C. Schmidt ◽  
J. Beyersdorfer ◽  
M. Simon-Najasek ◽  
C. Große ◽  
...  
Keyword(s):  
Electron Beam ◽  
High Resolution ◽  
Failure Analysis ◽  
Preparation Technique ◽  
Target Preparation ◽  
Material Analysis ◽  
Highly Efficient ◽  
Lock In

Abstract In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.

Sign in / Sign up

Export Citation Format

Share Document