Potential and electric field model for 18 nm SG tunnel field effect transistor

In this paper, a new source-all-around tunnel field-effect transistor (SAA-TFET) is proposed and investigated by using TCAD simulation. The tunneling junction in the SAA-TFET is divided laterally and vertically with respect to the channel direction which provides a relatively large tunneling junction area. An n+ pocket design is also introduced around the source to enhance tunneling rates and improve the device characteristics. In addition, the gate and n+ pocket region also overlap in the vertical and the lateral directions resulting in an enhanced electric field and, in turn, the ON-state current of the SAA-TFET is highly increased compared with the conventional TFET. Promising results in terms of DC (I ON , I OFF , ON/OFF current ratio and SS) and analog (cutoff frequency) performance are obtained for low (V DD = 0.5 V) and high (V DD = 1 V) supply voltages.

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Design of HeterojunctionTunnel Field-Effect Transistors with SiO2 isolation between Source and Drain for Low Power Application

10.21203/rs.3.rs-668005/v1 ◽

2021 ◽

Author(s):

Sweta Chander ◽

Sanjeet Kumar Sinha ◽

Prince Kumar Singh ◽

Ashish Kumar Singh

Keyword(s):

Electric Field ◽

Temperature Variation ◽

Field Effect ◽

Field Effect Transistor ◽

Field Effect Transistors ◽

Electrical Characteristics ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Output Characteristics ◽

Power Application

Abstract This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec. The validity of the proposed device has been done by Synopsys Sentaurus TCAD.

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An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b2253.098319 ◽

2019 ◽

Vol 8 (3) ◽

pp. 603-608 ◽

Cited By ~ 1

Keyword(s):

Electric Field ◽

Surface Potential ◽

Field Effect ◽

Analytical Modeling ◽

Field Effect Transistor ◽

Poisson Equations ◽

Dual Source ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Power Application

The given paper proposes the 2D analytical modeling of surface potential and electric field for a Dual Source Vertical Tunnel Field Effect Transistor (DSV-TFET). The 2-D Poisson equations are solved by parabolic approximation method, with the help of suitable boundary conditions and analytical expressions for surface potential and electric field distribution in DSV-TFET. The analytical results of proposed model are compared with simulation results drive using SILVACO TCAD tool, whereas in our proposed device DSV-TFET provides the high on current (ION=1.74×10-4 A/µm), low OFF current (IOFF= 6.92 ×10-13 A/µm), ION/IOFF current ratio in order of 108 to 109 with the minimum point of average subthreshold slope of 3.47 mV/decade which can be used for low power application.

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