Junction temperature estimation for an advanced active power cycling test

Author(s):  
U. M. Choi ◽  
F. Blaabjerg ◽  
S. Jorgensen
2021 ◽  
Vol 36 (3) ◽  
pp. 2661-2675
Author(s):  
Sebastian Baba ◽  
Andrzej Gieraltowski ◽  
Marek Jasinski ◽  
Frede Blaabjerg ◽  
Amir Sajjad Bahman ◽  
...  

Author(s):  
K. Sinha ◽  
M. Al-Bassyiouni ◽  
P. Hansen ◽  
A. Dasgupta ◽  
P. McCluskey ◽  
...  

When compared to temperature distributions in an actual application, thermal cycling is not a complete representation of the thermal gradients found in functional electronics under power-on condition. This discrepancy is particularly severe in power electronics and it distorts the thermo-mechanical stresses experienced at the joints and interfaces of power devices. Accelerated stress tests for power electronics are therefore better conducted with accelerated power cycling experiments rather than with accelerated thermal cycling, because the power cycles simulate more closely accelerated versions of an application cycle where the junction temperature of the die rises and falls as the power is turned off and on. However, developing a power cycling test setup can be comparatively more challenging than temperature cycling test setup, because of the complex triggering circuitry and logic needed for rapid power cycling, power circuitry needed to supply the large wattage safely to the devices under test, thermal cooling system to remove the high amount of heat generated, and software/hardware to control the test setup to maintain the right operational parameters. In this study, a test setup has been developed to power cycle IGBT and bipolar semiconductor devices for accelerated durability tests. The test setup is described and the role of each hardware and software component in the test setup is elaborated. Sample test results are presented, to illustrate the capabilities of the test setup. This work adds to the state of the art of power cycling experiments and improves our understanding of ways to develop stable power cycling test setups for various kinds of applications.


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Zoubir Khatir ◽  
Son-Ha Tran ◽  
Ali Ibrahim ◽  
Richard Lallemand ◽  
Nicolas Degrenne

AbstractExperimental investigations on the effects of load sequence on degradations of bond-wire contacts of Insulated Gate Bipolar Transistors power modules are reported in this paper. Both the junction temperature swing ($$\Delta T_{j}$$ Δ T j ) and the heating duration ($$t_{ON}$$ t ON ) are investigated. First, power cycling tests with single conditions (in $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON ), are performed in order to serve as test references. Then, combined power cycling tests with two-level stress conditions have been done sequentially. These tests are carried-out in the two sequences: low stress/high stress (LH) and high stress/low stress (HL) for both $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON . The tests conducted show that a sequencing in $$\Delta T_{j}$$ Δ T j regardless of the direction “high-low” or “low–high” leads to an acceleration of degradations and so, to shorter lifetimes. This is more pronounced when the difference between the stress levels is large. With regard to the heating duration ($$t_{ON}$$ t ON ), the effect seems insignificant. However, it is necessary to confirm the effect of this last parameter by additional tests.


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