Test Methodologies for Power Cycling Experiment

2009 ◽  
Author(s):  
K. Sinha ◽  
M. Al-Bassyiouni ◽  
P. Hansen ◽  
A. Dasgupta ◽  
P. McCluskey ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Power Electronics ◽  
Cooling System ◽  
Temperature Cycling ◽  
Junction Temperature ◽  
Stress Tests ◽  
Test Setup ◽  
Complete Representation ◽  
Cycling Test ◽  
Power Cycling

When compared to temperature distributions in an actual application, thermal cycling is not a complete representation of the thermal gradients found in functional electronics under power-on condition. This discrepancy is particularly severe in power electronics and it distorts the thermo-mechanical stresses experienced at the joints and interfaces of power devices. Accelerated stress tests for power electronics are therefore better conducted with accelerated power cycling experiments rather than with accelerated thermal cycling, because the power cycles simulate more closely accelerated versions of an application cycle where the junction temperature of the die rises and falls as the power is turned off and on. However, developing a power cycling test setup can be comparatively more challenging than temperature cycling test setup, because of the complex triggering circuitry and logic needed for rapid power cycling, power circuitry needed to supply the large wattage safely to the devices under test, thermal cooling system to remove the high amount of heat generated, and software/hardware to control the test setup to maintain the right operational parameters. In this study, a test setup has been developed to power cycle IGBT and bipolar semiconductor devices for accelerated durability tests. The test setup is described and the role of each hardware and software component in the test setup is elaborated. Sample test results are presented, to illustrate the capabilities of the test setup. This work adds to the state of the art of power cycling experiments and improves our understanding of ways to develop stable power cycling test setups for various kinds of applications.

Low-Temperature Joining Technique as Interconnection Technology for Power Electronics

2011 ◽  
Vol 324 ◽  
pp. 437-440
Author(s):  
Raed Amro
Keyword(s):  
Low Temperature ◽  
Power Electronics ◽  
Life Time ◽  
Junction Temperature ◽  
Limiting Factors ◽  
Power Devices ◽  
Packaging Technology ◽  
Power Cycling ◽  
Power Modules ◽  
Bond Wires

There is a demand for higher junction temperatures in power devices, but the existing packaging technology is limiting the power cycling capability if the junction temperature is increased. Limiting factors are solder interconnections and bond wires. With Replacing the chip-substrate soldering by low temperature joining technique, the power cycling capability of power modules can be increased widely. Replacing also the bond wires and using a double-sided low temperature joining technique, a further significant increase in the life-time of power devices is achieved.

Can Power Cycling Life of Solder Joint Interconnections be Assessed on the Basis of Temperature Cycling Tests?

1989 ◽  
Vol 111 (4) ◽  
pp. 310-312 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Fatigue Life ◽  
Solder Joint ◽  
Temperature Cycling ◽  
Cycling Test ◽  
Test Conditions ◽  
Power Cycling ◽  
Temperature Cycling Test ◽  
Cycling Life

We discuss how temperature cycling test conditions could be modified to be used for a tentative evaluation of the fatigue life of solder joint interconnections in surface mounted devices subjected to power cycling.

BGA Solder Life Prediction under Combined Power and Temperature Cycling Condition

2012 ◽  
Vol 2012 (1) ◽  
pp. 000531-000534 ◽  
Author(s):  
Fei Chai ◽  
Michael Osterman ◽  
Michael Pecht
Keyword(s):  
Ball Grid Array ◽  
Temperature Cycling ◽  
Temperature Cycle ◽  
Fatigue Reliability ◽  
Sac305 Solder ◽  
Cycling Test ◽  
Solder Interconnect ◽  
Power Cycling ◽  
Plastic Ball ◽  
Plastic Ball Grid Array

Solder interconnect failure is a known life limiting failure mechanism that is induced by cyclic temperature excursions. Thermal fatigue reliability of solder interconnects is conventionally assessed by simple temperature cycling test, which applies a constant temperature range, fixed dwell times and ramp rates during the test. However, due to the user controlled power cycles, non-constant workloads, and changes in the surrounding environment, electronics in the field often experience a complex combination of temperature and power cycling. In this study, the effect of power cycling superposed on a simple temperature cycling is experimentally examined. Furthermore, a scheme for modeling the solder interconnect fatigue life of Plastic Ball Grid Array (PBGA) parts under the concurrent power and temperature cycling. Damage, defined as the number of applied cycles over the number of survivable cycles, from the simple temperature cycle and the power cycle are linearly added using Miner's rule, and compared with the concurrent temperature and power cycling test. Cycles to failure of each condition is derived by life testing conducted on Plastic Ball Grid Array (PBGA) assembled with eutectic and SAC305 solder.

Thermal Management in High-Density High-Power Electronics Modules Using Thermal Pyrolytic Graphite

2020 ◽  
Vol 2020 (1) ◽  
pp. 000259-000263
Author(s):  
Riya Paul ◽  
Amol Deshpande ◽  
Fang Luo ◽  
Wei Fan
Keyword(s):  
Thermal Conductivity ◽  
Power Electronics ◽  
Cooling System ◽  
Substrate Surface ◽  
Pyrolytic Graphite ◽  
Temperature Drop ◽  
Vertical Direction ◽  
Junction Temperature ◽  
Power Module ◽  
Switching Losses

Abstract Tremendous effort is going on towards the packaging of power electronics modules to reduce the parasitic impedances and in turn, the voltage spikes during switching transients of power devices. The heat dissipated in terms of switching losses for high frequency applications need to be eliminated further to have some flexibility regarding the layout and, for the safe functioning of a power module by reducing junction temperature. Thermal pyrolytic graphite (TPG), with its high basal-plane thermal conductivity along the vertical direction helps direct heat towards the module bottom (cooling system), whereas its extremely low through-plane thermal conductivity along the horizontal direction guarantees minimum heat coupling among devices placed on the substrate surface. FEA simulations to verify thermal benefits of TPG and experimental results have been shown in this work which validates the junction temperature drop of up to 17 °C when using TPG as substrate and heat spreader compared with traditional materials.

Characterization of Die Stress Distributions in Area Array Flip Chip Packaging

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Power Cycling ◽  
Die Stress ◽  
On Chip ◽  
Test Chips

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions

2005 ◽  
Vol 128 (3) ◽  
pp. 281-284 ◽  
Author(s):  
Tong Hong Wang ◽  
Chang-Chi Lee ◽  
Yi-Shao Lai ◽  
Yu-Cheng Lin
Keyword(s):  
Thermal Analysis ◽  
Boundary Conditions ◽  
Thermal Cycling ◽  
Thermal Cycling Test ◽  
Transient Thermal Analysis ◽  
Cycling Test ◽  
Test Conditions ◽  
Power Cycling ◽  
Transient Thermal ◽  
Board Level

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

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