Analysis of Load Current Ripples in a Five Level Buck Converter

Author(s):  
Teo Hong Liang ◽  
Manickam Ramasamy ◽  
Mohamad Khan Afthan Ahmed Khan
Author(s):  
Syukri Bin Idham Halis ◽  
M.K.A. Ahamed Khan ◽  
Siti Nor Baizura bt Zawawi ◽  
Rohaizah Bt Mohd Ghazali ◽  
I. Elamvazuthi

Energies ◽  
2020 ◽  
Vol 13 (4) ◽  
pp. 856
Author(s):  
Jing-Yuan Lin ◽  
Yi-Chieh Hsu ◽  
Yo-Da Lin

In this paper, a triangular spread-spectrum mechanism is proposed to suppress the electromagnetic interference (EMI) of a DC-DC buck converter. The proposed triangular spread-spectrum mechanism, which is implemented in the chip, can avoid modifying the printed circuit board of switching regulators. In addition, a lower ripple of output voltage of switching regulators and a better system stability can be realized by the inductive DC resistance (DCR) current sensing circuit. The chip is fabricated by using TSMC 0.18-μm 1P6M CMOS technology. The chip area including PADs is 1.2 × 1.15 mm2. The input voltage range is 2.7~3.3 V and the output voltage is 1.8 V. The maximum load current is 700 mA. The off-chip inductor and capacitor are 3.3 μH and 10 μF, respectively. The experimental results demonstrate that the maximum spur of the proposed DC-DC buck converter with the triangular spread-spectrum mechanism improves to 14dBm. Moreover, the transient recovery time of step-up and step-down loads are both 5 μs. The measured maximum efficiency is 94% when the load current is 200 mA.


Sensors ◽  
2019 ◽  
Vol 19 (10) ◽  
pp. 2420 ◽  
Author(s):  
Sung Jin Kim ◽  
Dong Gyu Kim ◽  
Seong Jin Oh ◽  
Dong Soo Lee ◽  
Young Gun Pu ◽  
...  

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.


2019 ◽  
Vol 27 (2) ◽  
pp. 194-206
Author(s):  
Ismael Khaleel Murad

In this paper both synchronous and asynchronous buck-converter were designed to work in continuous conduction mode “CCM” and to deliver small load current. Then the two topologies were tested in terms of efficiency at small load current by use of  different values of switching frequencies (range from 150 KHz to 1MHz) and three separated values of duty-cycle (0.4, 0.6 and 0.8).   Obtained results turns out that efficiency of both synchronous and asynchronous buck-converter “switching step-down voltage regulator” responds in a negative manner to the increase in the switching frequency. However, this impact is being stronger in synchronous topology because of magnifying effect of losses related to switching frequency compared to those related to conduction when working at small load currents; this behavior makes obtained efficiency of both topologies in convergent levels when they operated to deliver small output current especially when working with higher switching frequencies. Larger duty-cycle can rise up the efficiency of both topologies.


Author(s):  
SUNG SIK PARK ◽  
JU SANG LEE ◽  
SANG DAE YU

This paper presents a new technique that adjusts the hysteresis window depending on the variations in load current caused by a voltage-mode circuit to reduce the voltage and current ripples. Moreover, a compact current-sensing circuit is used to provide an accurate sensing signal for achieving fast hysteresis window adjustment. In addition, a zero-current detection circuit is also proposed to eliminate the reverse current at light loads. As a result, this technique reduces the voltage ripple below 8.08 mVpp and the current ripple below 93.98 mApp for a load current of 500 mA. Circuit simulation is performed using 0.18 μm CMOS process parameters.


Author(s):  
Himadry Shekhar Das ◽  
Chee Wei Tan ◽  
AHM Yatim ◽  
Nik Din Bin Muhamad

Alternative energy technologies are being popular for power generation applications nowadays. Among others, Fuel cell (FC) technology is quite popular. However, the FC unit is costly and vulnerable to any disturbances in input parameters. Thus, to perform research and experimentation, Fuel cell emulators (FCE) can be useful. FCEs can replicate actual FC behavior in different operating conditions. Thus, by using it the application area can be determined. In this study, a FCE system is modelled using MATLAB/Simulink®. The FCE system consists of a buck DC-DC converter and a proportional integral (PI) based controller incorporating an electrochemical model of proton exchange membrane fuel cell (PEMFC). The PEMFC model is used to generate reference voltage of the controller which takes the load current as a requirement. The characteristics are compared with Ballard Mark V 5kW PEMFC stack specifications obtained from the datasheet. The results show that the FCE system is a suitable replacement of real PEMFC stack and can be used for research and development purpose.


2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
S. I. Serna-Garcés ◽  
R. E. Jiménez ◽  
C. A. Ramos-Paja

This paper proposes an active postfilter based on two Buck converters, connected in parallel, operating in complementary interleaving. In such a configuration the ripple in the load current could be virtually eliminated to improve the power quality in comparison with classical Point-Of-Load (POL) regulators based on a single Buck converter. The postfilter is designed to isolate the load from the main Buck regulator, leading to the proposed three-converter structure named BuckPS. The correct operation of the postfilter is ensured by means of a sliding-mode controller. Finally, the proposed solution significantly reduces the current harmonics injected into the load, and at the same time, it improves the overall electrical efficiency. Such characteristics are demonstrated by means of analytical results and illustrated using numerical results.


2020 ◽  
Vol 71 (2) ◽  
pp. 116-121
Author(s):  
Watson Valele ◽  
Robsen Virambath ◽  
Utkal Mehta ◽  
Sheikh Azid

AbstractThis paper presents the design and control of power electronic synchronous buck converter. Even though a synchronous buck converter is more popular and more widely available, it is not always efficient as nonsynchronous. Firstly, the inputoutput linearization from the state space averaging of the converter is studied, after which a small AC signal analysis is introduced to obtain the dynamic transfer function. All the parameters of the converter are calculated based on the output voltage, current ripples as well as the input voltage. For robustness, the controller is implemented by comparing the response of integer order with non-integer (fractional) order controller, simply known as fractional order controller (FOC). The fractional order derivative is implemented from the Oustaloup approximation and the controller parameters are being tuned using Nelder Mead approximation bases on a system model. It is shown that the FOC performance is comparatively better in presence of the load disturbances and parameter variations. The experimental study with the real-time fractional PI is possible to make for a stand-alone embedded application using FPAA. The proposed technique does not require any digitization of the signal, so it can be easy to implement with improved performance. The effectiveness of the analog controller is discussed, giving some future directions to adopt the new fractional controller.


Energies ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3809
Author(s):  
Pang-Jung Liu ◽  
Mao-Hui Kuo

A ripple-based constant on-time (RBCOT) buck converter with a virtual inductor current ripple (VICR) control can relax the stability constraint of large equivalent series resistance (ESR) at an output capacitor, but output regulation accuracy deteriorates due to the issue with output DC offset. Thus, this paper proposes a wave tracking reference (WTR) control to improve converter stability with low ESR and concurrently eliminate output DC offset on the regulated output voltage. Moreover, an adaptive on-time (AOT) circuit is presented to suppress the switching frequency variation with load current changes in continuous conduction mode. A prototype chip was fabricated in 0.35 µm CMOS technology for validation. The measurement results demonstrate that the maximum output DC offset is 4.1 mV and the output voltage ripple is as small as 3 mV. Furthermore, the switching frequency variation with the AOT circuit is 11 kHz when load current changes from 50 mA to 500 mA, and the measured maximum efficiency is 90.9% for the maximum output power of 900 mW.


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