scholarly journals Adaptive On-Time Buck Converter with Wave Tracking Reference Control for Output Regulation Accuracy

Energies ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3809
Author(s):  
Pang-Jung Liu ◽  
Mao-Hui Kuo

A ripple-based constant on-time (RBCOT) buck converter with a virtual inductor current ripple (VICR) control can relax the stability constraint of large equivalent series resistance (ESR) at an output capacitor, but output regulation accuracy deteriorates due to the issue with output DC offset. Thus, this paper proposes a wave tracking reference (WTR) control to improve converter stability with low ESR and concurrently eliminate output DC offset on the regulated output voltage. Moreover, an adaptive on-time (AOT) circuit is presented to suppress the switching frequency variation with load current changes in continuous conduction mode. A prototype chip was fabricated in 0.35 µm CMOS technology for validation. The measurement results demonstrate that the maximum output DC offset is 4.1 mV and the output voltage ripple is as small as 3 mV. Furthermore, the switching frequency variation with the AOT circuit is 11 kHz when load current changes from 50 mA to 500 mA, and the measured maximum efficiency is 90.9% for the maximum output power of 900 mW.

Energies ◽  
2020 ◽  
Vol 13 (4) ◽  
pp. 856
Author(s):  
Jing-Yuan Lin ◽  
Yi-Chieh Hsu ◽  
Yo-Da Lin

In this paper, a triangular spread-spectrum mechanism is proposed to suppress the electromagnetic interference (EMI) of a DC-DC buck converter. The proposed triangular spread-spectrum mechanism, which is implemented in the chip, can avoid modifying the printed circuit board of switching regulators. In addition, a lower ripple of output voltage of switching regulators and a better system stability can be realized by the inductive DC resistance (DCR) current sensing circuit. The chip is fabricated by using TSMC 0.18-μm 1P6M CMOS technology. The chip area including PADs is 1.2 × 1.15 mm2. The input voltage range is 2.7~3.3 V and the output voltage is 1.8 V. The maximum load current is 700 mA. The off-chip inductor and capacitor are 3.3 μH and 10 μF, respectively. The experimental results demonstrate that the maximum spur of the proposed DC-DC buck converter with the triangular spread-spectrum mechanism improves to 14dBm. Moreover, the transient recovery time of step-up and step-down loads are both 5 μs. The measured maximum efficiency is 94% when the load current is 200 mA.


Energies ◽  
2021 ◽  
Vol 14 (18) ◽  
pp. 5911
Author(s):  
Hsiao-Hsing Chou ◽  
Hsin-Liang Chen

This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.


Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1131 ◽  
Author(s):  
Mauricio Dalla Vecchia ◽  
Giel Van den Broeck ◽  
Simon Ravyts ◽  
Johan Driesen

This paper explores and presents the application of the Inductor–Diode and Inductor-Capacitor-Diode structures in a DC–DC step-down configuration for systems that require voltage adjustments. DC micro/picogrids are becoming more popular nowadays and the study of power electronics converters to supply the load demand in different voltage levels is required. Multiple strategies to step-down voltages are proposed based on different approaches, e.g., high-frequency transformer and voltage multiplier/divider cells. The key question that motivates the research is the investigation of the aforementioned Inductor–Diode and Inductor–Capacitor–Diode, current multiplier/divider cells, in a step-down application. The two-stage buck converter is used as a study case to achieve the output voltage required. To extend the intermediate voltage level flexibility in the two-stage buck converter, a second switch was implemented replacing a diode, which gives an extra degree-of-freedom for the topology. Based on this modification, three regions of operation are theoretically defined, depending on the operational duty cycles δ2 and δ1 of switches S2 and S1. The intermediate and output voltage levels are defined based on the choice of the region of operation and are mapped herein, summarizing the possible voltage levels achieved by each configuration. The paper presents the theoretical analysis, simulation, implementation and experimental validation of a converter with the following specifications; 48 V/12 V input-to-output voltage, different intermediate voltage levels, 100 W power rating, and switching frequency of 300 kHz. Comparisons between mathematical, simulation, and experimental results are made with the objective of validating the statements herein introduced.


2019 ◽  
Vol 27 (2) ◽  
pp. 194-206
Author(s):  
Ismael Khaleel Murad

In this paper both synchronous and asynchronous buck-converter were designed to work in continuous conduction mode “CCM” and to deliver small load current. Then the two topologies were tested in terms of efficiency at small load current by use of  different values of switching frequencies (range from 150 KHz to 1MHz) and three separated values of duty-cycle (0.4, 0.6 and 0.8).   Obtained results turns out that efficiency of both synchronous and asynchronous buck-converter “switching step-down voltage regulator” responds in a negative manner to the increase in the switching frequency. However, this impact is being stronger in synchronous topology because of magnifying effect of losses related to switching frequency compared to those related to conduction when working at small load currents; this behavior makes obtained efficiency of both topologies in convergent levels when they operated to deliver small output current especially when working with higher switching frequencies. Larger duty-cycle can rise up the efficiency of both topologies.


2021 ◽  
Vol 2 (2) ◽  
pp. 162-167
Author(s):  
Haris Masrepol ◽  
Muldi Yuhendri

Solar panels are a renewable energy power plant that uses sunlight as its main energy source. The power generated by solar panels are determined by the size of the solar panels, solar radiation and temperature. The power of the solar panels is also determined by the output voltage of the solar panels. To get the maximum output power at any time, it is necessary to adjust the output voltage of the solar panel. This study proposes controlling the maximum output power of solar panels, also known as maximum power point tracking (MPPT) by adjusting the output voltage of the solar panels using a buck converter. The buck converter output voltage regulation at the maximum power point of the solar panel is designed with the Perturbation and Observation (PO) algorithm which is implemented using an Arduino Mega 2560. This MPPT control system is applied to 4x50 Watt-Peak (WP) solar panels which are connected in parallel. The experimental results show that the proposed MPPT control system with the PO algorithm has worked well as expected. This can be seen from the output power generated by the solar panels already around the maximum power point at any change in solar radiation and temperature.


2016 ◽  
Vol 25 (11) ◽  
pp. 1650136 ◽  
Author(s):  
Zhaohan Li ◽  
Yongcheng Ji ◽  
Shu Yang ◽  
Yuchun Chang

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC–DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35[Formula: see text][Formula: see text]m BCDMOS 2P3M process, and the total size is 1.1[Formula: see text] 1.2[Formula: see text]mm2. The input range and output range of the converter are 6–30 V, and ([Formula: see text]–3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system.


Author(s):  
Simone Leeuw ◽  
◽  
Viranjay M. Srivastava

The traditional buck regulator provides the steady output voltage with high efficiency and low power dissipation. Various parameters of this regulator can be improved by the placement of Double-Gate (DG) MOSFET. The double-gate MOSFET provides twice the drain current flow, which improves the various parameters of buck regulator structure and inevitably increases the device performance and efficiency. In this research work, these parameters have been analyzed with implemented DG MOSFET buck regulator and realized the total losses 42.676 mW and efficiency 74.208%. This research work has designed a DG MOSFET based buck regulator with the specification of input voltage 12 V, output voltage 3.3 V, maximum output current 40 mA, switching frequency 100 kHz, ripple current of 10%, and ripple voltage of 1%.


Author(s):  
А.М. САЖНЕВ ◽  
Л.Г. РОГУЛИНА

Разработана модель имитационных испытаний электронного устройства в современной программной среде на основе отечественных компонентов. Проведены имитационные испытания конвертора напряжения на 24 В с выходным током 1,4 А, частотой коммутации 20 кГц и выпрямительного устройства с выходным напряжением 48 В, током нагрузки 28 А. Получены частотные зависимости уровней кондуктивных помех и выполнена их оценка на соответствие нормам. A model of simulation tests of an electronic device in a modern software environment based on domestic components has been developed. Simulation tests of a 24 V voltage converter with an output current of 1.4 A, a switching frequency of 20 kHz, and a rectifier device with an output voltage of 48 V, a load current of 28 A were carried out. The frequency dependences of conductive interference levels were obtained and their compliance with the standards was evaluated.


Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1451
Author(s):  
Po Li ◽  
Xiang Li ◽  
Tao Zeng

Interleaved DC-DC converters have been widely used in power conversion due to their high efficiency and reliability. In the application of new energy, this plays an increasingly important role in the grid-connected power generation of wind, solar, and tidal energy. Therefore, it is crucial to ensure the reliability and proper operation of interleaved DC-DC converters. We studied an open circuit fault (OCF) diagnosis method for a three-phase interleaved buck converter. We propose a non-invasive diagnosis method based on the output voltage using the harmonic amplitude and phase at the switching frequency as the diagnostic criteria. Evaluation was carried out on a hardware-in-the-loop (HIL) test platform to prove the validity of the proposed method. The results show that the presented method had high accuracy and robustness against OCFs, which could otherwise damage the system.


Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 960
Author(s):  
Myeong Woo Kim ◽  
Jae Joon Kim

This paper presents a dual-mode DC-DC buck converter including a load-dependent, efficiency-controllable scheme to support multi-purpose IoT applications. For light-load applications, a selectable adaptive on-time pulse frequency modulation (PFM) control is proposed to achieve optimum power efficiency by selecting the optimum switching frequency according to the load current, thereby reducing unnecessary switching losses. When the inductor peak current value or converter output voltage ripple are considered in some applications, its on-time can be adjusted further. In heavy-load applications, a conventional pulse width modulation (PWM) control scheme is adopted, and its gate driver is structured to reduce dynamic current, preventing the current from shooting through the power switch. A proposed dual-mode buck converter prototype is fabricated in a 180 nm CMOS process, achieving its measured maximum efficiency of 95.7% and power density of 0.83 W/mm2.


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