Effective power and ground distribution scheme for deep submicron high speed VLSI circuits

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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Modeling the substrate effect in interconnect line characteristics of high-speed VLSI circuits

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/22.721145 ◽

1998 ◽

Vol 46 (10) ◽

pp. 1436-1443 ◽

Cited By ~ 32

Author(s):

Jae-Kyung Wee ◽

Young-June Park ◽

Hong-Shick Min ◽

Dae-Hyung Cho ◽

Man-Ho Seung ◽

...

Keyword(s):

High Speed ◽

Vlsi Circuits ◽

Substrate Effect

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Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating

National Academy Science Letters ◽

10.1007/s40009-019-00848-4 ◽

2019 ◽

Vol 43 (3) ◽

pp. 229-232 ◽

Cited By ~ 1

Author(s):

T. Thamaraimanalan ◽

P. Sampath

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Power Gating

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Study on the Application of Marine Biodiesel on High Speed Diesel Engines

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.287-290.1976 ◽

2011 ◽

Vol 287-290 ◽

pp. 1976-1979

Author(s):

Lin Cai Ma ◽

Zhi Guo Zhou ◽

Liang Yao Xia ◽

Da Xue Liu ◽

Xiao Li Yu

Keyword(s):

Diesel Engine ◽

High Speed ◽

Consumption Rate ◽

Effective Power ◽

Engine Load ◽

Bench Tests ◽

Fuel Consumption Rate ◽

High Speed Diesel ◽

Hc Emissions ◽

Load Conditions

A bench tests were carried out on an YC6J190 diesel engine fueled with B20 marine biodiesel. The results showed that the engine’s effective power decreased by 1.8%, the fuel consumption rate increased by 0.07%, HC emissions decreased by 19.17% and the soot decreased by 25% as average under full engine load conditions. HC decreased by 23.4% and the soot decreased by 23% as average under part engine load conditions. The soot emissions decreased by 28.8% as average under the free acceleration conditions.

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Implementation of time efficient hybrid multiplier for FFT computation

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.7.10755 ◽

2018 ◽

Vol 7 (2.7) ◽

pp. 409 ◽

Cited By ~ 1

Author(s):

R Nikhil ◽

G V. S. Veerendra ◽

J Rahul M. S. Sri Harsha ◽

Dr V. S. V. Prabhakar

Keyword(s):

Power Efficiency ◽

High Speed ◽

Vlsi Circuits ◽

Low Power Consumption ◽

Chip Area ◽

Booth Multiplier ◽

Low Delay ◽

Wallace Tree ◽

Wallace Tree Multiplier ◽

Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.

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PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOGUE VLSI MLPs

Journal of Circuits System and Computers ◽

10.1142/s0218126696000108 ◽

1996 ◽

Vol 06 (02) ◽

pp. 93-113 ◽

Cited By ~ 1

Author(s):

GRAHAM CAIRNS ◽

LIONEL TARASSENKO

Keyword(s):

High Speed ◽

Vlsi Circuits ◽

Benchmark Problems ◽

Perturbation Techniques ◽

Successful Operation ◽

Reliable Performance ◽

Analogue Vlsi ◽

Computationally Intensive ◽

On Chip ◽

Simple Integration

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.

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