PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOGUE VLSI MLPs

1996 ◽  
Vol 06 (02) ◽  
pp. 93-113 ◽  
Author(s):  
GRAHAM CAIRNS ◽  
LIONEL TARASSENKO
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Benchmark Problems ◽  
Perturbation Techniques ◽  
Successful Operation ◽  
Reliable Performance ◽  
Analogue Vlsi ◽  
Computationally Intensive ◽  
On Chip ◽  
Simple Integration

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.

A Survey Addressing on High Performance On-Chip VLSI Interconnect

2013 ◽  
Vol 59 (3) ◽  
pp. 307-312 ◽  
Author(s):  
C. Mohamed Yousuff ◽  
V. Mohamed Yousuf Hasan ◽  
M. R. Khan Galib
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
State Of The Art ◽  
Vlsi Circuits ◽  
Cmos Circuits ◽  
Delay Optimization ◽  
High Speed Design ◽  
On Chip ◽  
Very High

Abstract With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.

scholarly journals A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2637
Author(s):  
Ignacio Pérez ◽  
Miguel Figueroa
Keyword(s):  
Image Classification ◽  
High Speed ◽  
Hardware Acceleration ◽  
Graphics Processors ◽  
Embedded Processor ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Computationally Intensive ◽  
On Chip

Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of 224×224 pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

High-Speed On-Chip Event Counters for Embedded Systems

2009 ◽  
Author(s):  
Nilanjan Mukherjee ◽  
Artur Pogiel ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Embedded Systems ◽  
High Speed ◽  
On Chip

Removal Mechanism of Titanium Alloy Ti6Al4V Based on Single-Grain High Speed Grinding Test

2011 ◽  
Vol 487 ◽  
pp. 39-43 ◽  
Author(s):  
L. Tian ◽  
Yu Can Fu ◽  
W.F. Ding ◽  
Jiu Hua Xu ◽  
H.H. Su
Keyword(s):  
Titanium Alloy ◽  
High Speed ◽  
Chip Thickness ◽  
Wheel Speed ◽  
High Speed Grinding ◽  
Tc4 Alloy ◽  
Grinding Mechanism ◽  
Single Grain ◽  
On Chip ◽  
Titanium Alloy Ti6al4v

Single-grain grinding test plays an important part in studying the high speed grinding mechanism of materials. In this paper, a new method and experiment system for high speed grinding test with single CBN grain are presented. In order to study the high speed grinding mechanism of TC4 alloy, the chips and grooves were obtained under different wheel speed and corresponding maximum undeformed chip thickness. Results showed that the effects of wheel speed and chip thickness on chip formation become obvious. The chips were characterized by crack and segment band feature like the cutting segmented chips of titanium alloy Ti6Al4V.

scholarly journals Thermographic Study of Chip Temperature in High-Speed Dry Milling Magnesium Alloys

2016 ◽  
Vol 7 (2) ◽  
pp. 86-92 ◽  
Author(s):  
Józef Kuczmaszewski ◽  
Ireneusz Zagórski ◽  
Piotr Zgórniak
Keyword(s):  
Temperature Measurement ◽  
Magnesium Alloys ◽  
High Speed ◽  
Machining Process ◽  
Dry Milling ◽  
Technological Parameters ◽  
Chip Temperature ◽  
Thermographic Study ◽  
On Chip ◽  
The Impact

Abstract This paper presents an overview of the state of knowledge on temperature measurement in the cutting area during magnesium alloy milling. Additionally, results of own research on chip temperature measurement during dry milling of magnesium alloys are included. Tested magnesium alloys are frequently used for manufacturing elements applied in the aerospace industry. The impact of technological parameters on the maximum chip temperature during milling is also analysed. This study is relevant due to the risk of chip ignition during the machining process.

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