scholarly journals High Speed Pilot-less Sampling Frequency Acquisition for DMT Systems

2005 ◽  
Author(s):  
Ching-Chi Chang ◽  
Chorng-Kuang Wang
Keyword(s):  
High Speed ◽  
Sampling Frequency

High Speed Under-Sampling Frequency Measurements on FPGA

2017 ◽  
Vol 7 (3) ◽  
pp. 1316
Author(s):  
Seyed Ehsan Yasrebi Naeini ◽  
Ali Maroosi
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Sampling Rate ◽  
Sampling Frequency ◽  
Phase Changes ◽  
Frequency Measurements ◽  
Frequency Detection ◽  
Field Programmable ◽  
Under Sampling ◽  
Nyquist Rate

A Sampling rate is less than Nyquist rate in some applications because of hardware limitations. Consequently, extensive researches have been conducted on frequency detection from sub-sampled signals. Previous studies on under-sampling frequency measurements have mostly discussed under-sampling frequency detection in theory and suggested possible methods for fast under-sampling frequencies detection. This study examined few suggested methods on Field Programmable Gate Array (FPGA) for fast under-sampling frequencies measurement. Implementation of the suggested methods on FPGA has issues that make them improper for fast data processing. This study tastes and discusses different methods for frequency detection including Least Squares (LS), Direct State Space (DSS), Goertzel filter, Sliding DFT, Phase changes of Fast Furrier Transform (FFT), peak amplitude of FFT to conclude which one from these methods are suitable for fast under-sampling frequencies detection on FPGA. Moreover, our proposed approach for sub-sampling detection from real waveform has less complextity than previous approaches from complex waveform.

Integral Type Multi-Ramp for Single-Slope ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1908-1912 ◽  
Author(s):  
Nan Lyu ◽  
Ning Mei Yu ◽  
He Jiu Zhang
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Supply Voltage ◽  
High Accuracy ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Voltage Reference ◽  
Integral Type ◽  
Power Supply Voltage ◽  
The One

This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.

A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS

2003 ◽  
Vol 12 (05) ◽  
pp. 643-654 ◽  
Author(s):  
YONG LIAN
Keyword(s):  
Frequency Response ◽  
High Speed ◽  
Sampling Frequency ◽  
Fir Filters ◽  
Throughput Rate ◽  
Shaping Filter ◽  
Filter Structure ◽  
Frequency Response Masking ◽  
Digital Fir Filters ◽  
Frm Approach

This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

scholarly journals Comparison of external load on high speed actions in friendly macth and training sessions (Comparación de carga externa en las acciones de alta velocidad en paridos amistosos y sesiones de entrenamientos)

Retos ◽  
2017 ◽  
pp. 54-57
Author(s):  
Francisco Javier Toscano Bendala ◽  
Miguel Angel Campos Vázquez ◽  
Luis Jesús Suarez-Arrones ◽  
Francisco Javier Núñez Sánchez
Keyword(s):  
High Velocity ◽  
External Load ◽  
High Speed ◽  
Sampling Frequency ◽  
Soccer Players ◽  
Professional Soccer ◽  
Soccer Team ◽  
Gps Devices ◽  
And Training

The aim of the current research was to find out the differences that exist between the external load in high-velocity actions (SP+) in competitions and in training sessions of professional soccer team. We took as SP+ indicators those actions that the soccer players performed over 23 km·h-1 and could be held for at least 1 second. It was monitored 25 professional players belonging to the first team of a team of the first Spanish soccer division, and were used 10 GPS devices were used (SPI, ELITE model, GPSport, Canberra, Australia). These GSPORT transmitters have a sampling frequency of 1 Hz. The results of our study showed how during the game, the players performed substantially more number of SP+ de 1 s, 2 s, 3 s y 4 s (per minute of activity) than during training.Resumen.  El objetivo de esta investigación fue encontrar las diferencias que existen entre la carga externa en acciones de alta velocidad (SP+) en paridos amistosos de pretemporada y las sesiones de entrenamientos en un equipo de fútbol profesional. Tomamos como indicadores SP + aquellas acciones que realizan los jugadores de fútbol por encima de 23 km·h-1 y pudiendo ser mantenidas durante al menos 1 segundo. Se monitorizaron 25 jugadores profesionales pertenecientes a la primera plantilla de un equipo de la primera división de fútbol español, y se utilizaron 10 dispositivos GPS (SPI, ELITE model, GPSport, Canberra, Australia). Estos transmisores GPSORT, tienen una frecuencia de muestreo de 1 Hz. Los resultados de nuestro estudio manifestaron como durante el partido, los jugadores realizaron de manera sustancial más número de SP+ de 1 s, 2 s, 3 s y 4 s (por minuto de actividad) que durante los entrenamientos.

Ultrasonic Phased Array Industrial Imaging with Sub-Nyquist Sampling Rate

2013 ◽  
Vol 347-350 ◽  
pp. 327-331
Author(s):  
Guang Zhi Dai ◽  
Guo Qiang Han ◽  
Xian Yue Ouyang
Keyword(s):  
High Speed ◽  
Phased Array ◽  
Signal To Noise Ratio ◽  
Signal Reconstruction ◽  
Sampling Rate ◽  
Sampling Frequency ◽  
Frequency Resolution ◽  
Signal Frequency ◽  
Beam Focusing ◽  
Ultrasonic Phased Array

this paper uses a new type of FRI (Finite Rate of Innovation) sampling pattern based Sub-Nyquist sampling model breaked through Shannon theorem that it can get accurate signal reconstruction based on signal information rate, which requires the sampling frequency lower than two times the max signal frequency. We apply the new model in the ultrasonic phased array industrial imaging. In the experiment, ultrasonic phased array realized dynamic focusing and the high speed scan by ultrasonic array transducer of various array time delays to get flexible controllable synthesis beam composed signals that received by 32 phased array elements . The results indicate that in the model it greatly reduces the signal sampling frequency and improves the signal-to-noise ratio, frequency resolution at the same of the beam focusing and steering flexible.

The Influence of Sampling Frequency on the Results of Motion Analysis Performed by High-Speed Digital Image Correlation

2015 ◽  
Vol 816 ◽  
pp. 397-403 ◽  
Author(s):  
Martin Hagara ◽  
Róbert Huňady
Keyword(s):  
Digital Image Correlation ◽  
Correlation Analysis ◽  
Experimental Determination ◽  
Digital Image ◽  
High Speed ◽  
Sampling Frequency ◽  
Image Correlation ◽  
Correlation System

The paper describes an experimental determination of kinematic quantities using high-speed digital image correlation system. It deals with the analysis of minimal sampling frequency needed for correctly performed high-speed correlation analysis. The authors also describe the influence of cameras sampling frequency on the quality of the obtained results. Mentioned analysis was performed using a rotational object. For the purposes of the results comparison the data obtained from correlation system in a form of displacements in three mutually perpendicular directions were processed in Matlab and in the paper are depicted in a form of graphical visualizations.

Research on the High-Speed Data Acquisition System Based on Clock Distribution

2013 ◽  
Vol 834-836 ◽  
pp. 1039-1046
Author(s):  
Guo Zhong Yao ◽  
Li Si Ai ◽  
Li Zhong Shen ◽  
Gui Yong Wang
Keyword(s):  
Data Acquisition ◽  
High Frequency ◽  
High Speed ◽  
Design Method ◽  
Sampling Frequency ◽  
Clock Distribution ◽  
High Speed Adc ◽  
Distribution Mode ◽  
High Speed Data Acquisition ◽  
High Speed Data

In order to digitize the signal of high frequency or ultra-high frequency, clock distribution technology with the same frequency but different phase is utilized as a solution to this difficulty. The principles of high-speed analog-to-digit converter (ADC) by the lower rate ADC module, key technology and key module of the data acquisition systems are studied. From the aspects of system architecture, clock distribution module based on the AD9520, ADC module based on the AD9480 and data processing, the design method of ultra-high-speed ADC by clock distribution mode are explored. The results show that: driving many ADC modules with serial clocks of the same frequency but different phase in parallel to sample the same signal, the sampling frequency of the ADC system is the sum of each ADC sampling frequency. Four AD9480 modules are driven by four-way 250MHz clocks with phase fault 90°, respectively. And 1GHz samples per second can be attained, which is four times of the sampling frequency by monolithic AD9480.

FPGA – ARM Heterogeneous System for High Speed Signal Analysis

2011 ◽  
Vol 180 ◽  
pp. 207-213 ◽  
Author(s):  
Ernest Jamro ◽  
Maciej Wielgosz ◽  
Sławomir Bieniasz ◽  
Witold Cioch
Keyword(s):  
Processing Speed ◽  
Signal Analysis ◽  
High Speed ◽  
Sampling Frequency ◽  
Diagnostic Systems ◽  
Digital Signals ◽  
Gate Arrays ◽  
Analog Signals ◽  
Arm Microprocessor ◽  
Programmable Gate Arrays

This paper presents a version 2 of hardware solution denoted as Programmable Unit for Diagnostic (PUD-2) based on Filed Programmable Gate Arrays (FPGAs) and ARM-based OMAP3530 microprocessor adapted for diagnostic systems. The sampling frequency of the input analog signals and digital signals processing speed of the PUD is high beyond comparable DSP based systems. Employing ARM microprocessor allows for much quicker and easer design than only FPGA-based solution.

scholarly journals A Fast Storage Method for Drone-Borne Passive Microwave Radiation Measurement

Sensors ◽  
2021 ◽  
Vol 21 (20) ◽  
pp. 6767
Author(s):  
Xiangkun Wan ◽  
Xiaofeng Li ◽  
Tao Jiang ◽  
Xingming Zheng ◽  
Xiaojie Li ◽  
...  
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Microwave Radiometer ◽  
Sampling Frequency ◽  
Continuous Data ◽  
Radio Frequency Interference ◽  
Radiation Measurement ◽  
Time Sharing ◽  
Time Consumption ◽  
Programming Step

A drone-borne microwave radiometer requires a high sampling frequency and a continuous acquisition capability to detect and mitigate radio frequency interference (RFI), but existing methods cannot store such a large amount of data. In this paper, the dual polling write method (DPSM) for secure digital cards triggered by a timer under a multitask framework based on STM32 MCU is proposed to meet the requirements of continuous data storage. The card programming step was changed from a query waiting structure to a polling query flag bit structure, and time-sharing processing and parallel processing were used to simulate multithreading. The experimental results were as follows: (1) the time consumption of the whole storage procedure was reduced from 4000 microseconds to 200–400 microseconds; (2) the time consumption of the card programming step was reduced from 3000 microseconds in the first block and 1000 microseconds in the second and subsequent blocks to 17–174 microseconds and 18–71 microseconds, respectively, compared with the existing method; (3) the delay in the whole sampling cycle was reduced from 3942 microseconds to 0 microseconds. The results of this paper can meet the data storage requirements of a drone-borne microwave radiometer and be applied to the high-speed storage of other devices.

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