Integral Type Multi-Ramp for Single-Slope ADC
2013 ◽
Vol 303-306
◽
pp. 1908-1912
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This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.
2014 ◽
Vol 989-994
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pp. 1165-1168
2011 ◽
Vol 20
(01)
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pp. 15-27
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2018 ◽
Vol 27
(07)
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pp. 1850105
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2018 ◽
Vol 27
(07)
◽
pp. 1850116
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2012 ◽
Vol 256-259
◽
pp. 2373-2378
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