scholarly journals Design and Realization of an Aviation Computer Micro System Based on SiP

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 766
Author(s):  
Hao Lv ◽  
Shengbing Zhang ◽  
Wei Han ◽  
Yongqiang Liu ◽  
Shuo Liu ◽  
...  
Keyword(s):  
Computer System ◽  
Flash Memory ◽  
Heat Dissipation ◽  
Signal Integrity ◽  
Reference Value ◽  
Test Method ◽  
Ultra Low Power ◽  
Eye Diagram ◽  
Integrated Microsystems ◽  
On Chip

In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity.

A Test Method and Test Codes Generator for Improved HT Fault Model Based on NoC

2015 ◽  
Vol 724 ◽  
pp. 327-333
Author(s):  
Yu Zhu Zhang ◽  
Yi Gang He ◽  
Li Fen Yuan ◽  
Mao Xu Liu
Keyword(s):  
Signal Integrity ◽  
Fault Model ◽  
Simulation Software ◽  
Test Method ◽  
Pspice Simulation ◽  
Model Based ◽  
Test Circuit ◽  
On Chip ◽  
Test Requirements

NoC is a expand for SoC.The architecture of NoC is huge and complex,it leads to the crosstalk fault between internal transmission of NoC increasingly serious. Crosstalk serious impact on the signal integrity of on-chip system.A new test codes generator was designed by PSpice simulation software based on improved HT model. The generator was composed of a 16-bit counter and a 16-bit data selector.The generator was tested by PSpice software,the result showed that it satisfied the test requirements and had the advantage of portable. A crossstalk test method was proposed in this paper,we used this method on a test circuit,the result showed that the method could reduce the number of tests and save resource effectively.

scholarly journals ThermalAttackNet: Are CNNs Making It Easy to Perform Temperature Side-Channel Attack in Mobile Edge Devices?

2021 ◽  
Vol 13 (6) ◽  
pp. 146
Author(s):  
Somdip Dey ◽  
Amit Kumar Singh ◽  
Klaus McDonald-Maier
Keyword(s):  
Information Flow ◽  
Heat Dissipation ◽  
Side Channel ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Information Flow Control ◽  
On Chip ◽  
Temperature Side ◽  
Over Time ◽  
Memory Efficient

Side-channel attacks remain a challenge to information flow control and security in mobile edge devices till this date. One such important security flaw could be exploited through temperature side-channel attacks, where heat dissipation and propagation from the processing cores are observed over time in order to deduce security flaws. In this paper, we study how computer vision-based convolutional neural networks (CNNs) could be used to exploit temperature (thermal) side-channel attack on different Linux governors in mobile edge device utilizing multi-processor system-on-chip (MPSoC). We also designed a power- and memory-efficient CNN model that is capable of performing thermal side-channel attack on the MPSoC and can be used by industry practitioners and academics as a benchmark to design methodologies to secure against such an attack in MPSoC.

Signal Integrity and Reliability of Network-on-Chip

2018 ◽  
pp. 191-234
Author(s):  
Santanu Kundu ◽  
Santanu Chattopadhyay
Keyword(s):  
Signal Integrity ◽  
Network On Chip ◽  
On Chip

scholarly journals Design and Implementation of Smart Non-Invasive Bone Conduction Ear-Plug System

2018 ◽  
Vol 9 (2) ◽  
pp. 249
Author(s):  
Ravichandran G ◽  
M Krishnamurthy
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Performance ◽  
Bone Conduction ◽  
Ultra Low Power ◽  
Audio Processing ◽  
Activity Tracker ◽  
Non Invasive ◽  
Run Up ◽  
Music Player

<p>The project aim is to design a smart earplug system integrated with non-invasive bone conduction technique which is capable of doing some advanced audio processing to provide voice enhancing, noise filtered audio for the hearing impaired people [2]. The system is also designed to work as an embedded music player, a life activity tracker and a Smartphone companion. It can even read the SMS that is just received on your smartphone into your ear. This project needs a very low power microcontroller but with high-performance signal processing requirements. STM32L476 from STMicroelectronics meets this needs and thus chosen as the main MCU. It is an ultra-low power ARM Cortex-M4 based microcontroller that can run up to 80MHz.  It has got 1MB of Flash memory and 128 KB RAM.</p>

Evolutionary design of high signal integrity interconnection based on eye-diagram

2018 ◽  
Vol 23 (3) ◽  
pp. 298-303 ◽  
Author(s):  
Tetsuya Odaira ◽  
Naoki Yokoshima ◽  
Ikuo Yoshihara ◽  
Moritoshi Yasunaga
Keyword(s):  
Signal Integrity ◽  
Evolutionary Design ◽  
High Signal ◽  
Eye Diagram

scholarly journals A Comparative Study of the CMT+P Process on 316L Stainless Steel Additive Manufacturing

2020 ◽  
Vol 10 (9) ◽  
pp. 3284 ◽  
Author(s):  
Bin Xie ◽  
Jiaxiang Xue ◽  
Xianghui Ren ◽  
Wei Wu ◽  
Zhuangbin Lin
Keyword(s):  
Tensile Strength ◽  
Stainless Steel ◽  
Additive Manufacturing ◽  
Tensile Test ◽  
Heat Dissipation ◽  
316L Stainless Steel ◽  
Single Channel ◽  
Steel Wire ◽  
Energy Dispersive Spectrometer ◽  
Test Method

Adopting the cold metal transfer plus pulse (CMT + P) process, 316L stainless steel wire was treated with a single channel multi-layer deposition experiment under different linear energy. The microstructures of different regions on the deposited samples were observed by optical microscope and scanning electron microscope, and the element distribution in the structure was analyzed by energy dispersive spectrometer. The mechanical properties and microhardness were measured by tensile test method and microhardness tester, respectively, and the anisotropy of tensile strength in horizontal and vertical directions were calculated. Finally, the fracture morphology of the tensile samples were observed by SEM. Experiment results showed that when the difference between the actual and the optimal wire feeding speed matching the specific welding speed was too large, this led to an unstable deposition process as well as flow and collapse of weld bead metal, thus seriously deteriorating the appearance of the deposition samples. The results from metallographic micrograph showed that rapid heat dissipation of the substrate caused small grains to generate in the bottom region of deposition samples, then gradually grew up to coarse dendrites along the building direction in the middle and top region caused by the continuous heat accumulation during deposition. Tensile test results showed that with the increase of linear energy, the horizontal and vertical tensile strength of the as-deposited samples decreased. In addition, the higher linear energy would deteriorate the microstructure of as-deposited parts, including significantly increasing the tendency of oxidation and material stripping. The microhardness values of the bottom, middle and top regions of the samples fluctuated along the centerline of the cross-section, and the values showed a trend of decreasing first and then rising along the building direction. Meanwhile, the yield strength and tensile strength of each specimen showed obvious anisotropy due to unique grain growth morphology. On the whole, the results from this study prove that CMT+P process is a feasible MIG welding additive manufacturing method for 316L stainless steel.

Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

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